Abstract: Multiplier circuit for multiplying an information signal x(t) by a periodic signal y(t) having frequency f.sub.o, more specifically for amplitude modulation purposes in a stereo decoder. The multiplier circuit comprises N switching circuits 21(k) wherein k=0, 1, . . . N-1 which are each connected to a clock pulse generator 221, 222 by means of a control channel 25(k) and are each connected to an input of an adder device 28 by means of a signal channel 26(k). In addition, each switching circuit 21(k) receives the information signal x(t). A series of clock pulses g(k;t) is applied to each control channel in such a manner that for the control channel having number k these clock pulses occur at the instants t.sub.o +k(T.sub.o /N)+iT.sub.o wherein t.sub.o represents a constant T.sub.o =1/f.sub.o and i=. . . , -2, -1, 0, 1, 2, . . . Each signal channel 26(k) comprises a weighting network 27(k) having a constant weighting factor W(k) defined by the relation W(k)=y(t.sub.o +k(T.sub.o /N)).

Abstract: Stereo decoder for multiplex signals comprising a demultiplexer for decoding the left-hand and the right-hand sound signal of a stereo multiplex signal, a phase-locked loop which includes a phase-locked oscillator and a multiplicative phase detector, and a pilot elimination circuit, for reducing the pilot signal of a multiplex signal, which is used in two manners, namely, to suppress the pilot signal in the decoded left-hand and right-hand sound signal at the sound output of the demultiplexer, and to suppress disturbances in the frequency control of the phase-locked oscillator caused by sound components of the multiplex signal. To this end the phase detector comprises a differential reference input stage to which on the one hand the complete stereo multiplex signal is applied and on the other hand, in phase (common mode) therewith, the output signal of the pilot elimination circuit, that is to say the stereo multiplex signal with the suppressed pilot signal.