Patents by Inventor Albert J. Van Norstrand, Jr.
Albert J. Van Norstrand, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170344368Abstract: Methods and apparatus for identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor including receiving, by an instruction fetch unit of the processor, the interrupt ITAG; retrieving an effective address table (EAT) row from an EAT, wherein the EAT row comprises a range of EAs and a first ITAG of a range of ITAGs; accessing a processor instruction vector comprising a plurality of elements, each element corresponding to one of a plurality of ITAGs; applying a mask to the processor instruction vector to obtain a portion of the processor instruction vector that begins with an element corresponding to the first ITAG and is defined by an element corresponding to the interrupt ITAG; calculating an EA offset; and identifying the EA for the interrupt ITAG using the EA offset and the range of EAs in the retrieved EAT row.Type: ApplicationFiled: May 31, 2016Publication date: November 30, 2017Inventors: DAVID S. LEVITAN, MEHUL PATEL, ALBERT J. VAN NORSTRAND, Jr., PHILLIP G. WILLIAMS
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Publication number: 20170344378Abstract: Methods and apparatus for managing an effective address table (EAT) in a multi-slice processor including receiving, from an instruction sequence unit, a next-to-complete instruction tag (ITAG); obtaining, from the EAT, a first ITAG from a tail-plus-one EAT row, wherein the EAT comprises a tail EAT row that precedes the tail-plus-one EAT row; determining, based on a comparison of the next-to-complete ITAG and the first ITAG, that the tail EAT row has completed; and retiring the tail EAT row based on the determination.Type: ApplicationFiled: July 27, 2016Publication date: November 30, 2017Inventors: AKASH V. GIRI, DAVID S. LEVITAN, MEHUL PATEL, ALBERT J. VAN NORSTRAND, JR.
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Publication number: 20170315810Abstract: A technique for operating a processor includes identifying a difficult branch instruction (branch) whose target address (target) has been mispredicted multiple times. Information about the branch (which includes a current target and a next target) is learned and stored in a data structure. In response to the branch executing subsequent to the storing, whether a branch target of the branch corresponds to the current target in the data structure is determined. In response to the branch target of the branch corresponding to the current target of the branch in the data structure, the next target of the branch that is associated with the current target of the branch in the data structure is determined. In response to detecting that a next instance of the branch has been fetched, the next target of the branch is utilized as the predicted target for execution of the next instance of the branch.Type: ApplicationFiled: April 28, 2016Publication date: November 2, 2017Inventors: RICHARD J. EICKEMEYER, NAGA P. GORTI, DAVID S. LEVITAN, ALBERT J. VAN NORSTRAND, JR.
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Patent number: 9798549Abstract: An instruction sequencing unit in an out-of-order (OOO) processor includes a Most Favored Instruction (MFI) mechanism that designates an instruction as an MFI. The processing queues in the processor identify when they contain the MFI, and assures processing the MFI. The MFI remains the MFI until it is completed or is flushed, and which time the MFI mechanism selects the next MFI.Type: GrantFiled: October 31, 2016Date of Patent: October 24, 2017Assignee: International Business Machines CorporationInventors: Maarten J. Boersma, Robert A. Cordes, David A. Hrusecky, Jennifer L. Molnar, Brian W. Thompto, Albert J. Van Norstrand, Jr., Kenneth L. Ward
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Publication number: 20170277535Abstract: A technique for operating a processor includes receiving, by a history buffer, a flush tag associated with an oldest instruction to be flushed from a processor pipeline. In response to the flush tag being older than a first instruction tag that identifies a first instruction associated with a current value stored in a register of the register file and younger than a second instruction tag that identifies a second instruction associated with a previous value that was stored in the register of the register file, the history buffer transfers the previous value for the register to the register file. In response to the flush tag not being older than the first instruction tag and younger than the second instruction tag, the history buffer does not transfer the previous value for the register to the register file (as such, the register maintains the current value following a pipeline flush).Type: ApplicationFiled: March 24, 2016Publication date: September 28, 2017Inventors: HUNG Q. LE, DAVID S. LEVITAN, DUNG Q. NGUYEN, ALBERT J. VAN NORSTRAND, JR.
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Publication number: 20170262281Abstract: Methods and apparatus for thread migration using a microcode engine of a multi-slice processor including issuing a thread migration instruction to the microcode engine of a decode unit, the thread migration instruction comprising an indication that the thread migration instruction is to be processed by the microcode engine; decoding, by the microcode engine, the thread migration instruction into a plurality of internal operations each targeting a different register entry; transmitting the plurality of internal operations to a dispatcher of the multi-slice processor; and manipulating, by the multi-slice processor, a plurality of register entries according to the plurality of internal operations.Type: ApplicationFiled: March 14, 2016Publication date: September 14, 2017Inventors: JAMES W. BISHOP, MARCY E. BYERS, STEVEN R. CARLOUGH, PAUL M. KENNEDY, ALBERT J. VAN NORSTRAND, JR., PHILLIP G. WILLIAMS
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Publication number: 20170262286Abstract: Blocking instruction fetching in a computer processor, includes: receiving a non-branching instruction to be executed by the computer processor; determining whether executing the non-branching instruction will cause a flush; and responsive to determining that executing the non-branching instruction will cause a flush, disabling instruction fetching for the computer processor for a time, including recoding the instruction such that the recoded instruction will be interpreted by an instruction fetch unit as an unconditional branch instruction.Type: ApplicationFiled: March 8, 2016Publication date: September 14, 2017Inventors: BRYAN G. HICKERSON, SHELDON LEVENSTEIN, DAVID S. LEVITAN, ALBERT J. VAN NORSTRAND, JR.
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Publication number: 20170168945Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.Type: ApplicationFiled: February 18, 2016Publication date: June 15, 2017Inventors: SUNDEEP CHADHA, ROBERT A. CORDES, DAVID A. HRUSECKY, HUNG Q. LE, JENTJE LEENSTRA, DUNG Q. NGUYEN, BRIAN W. THOMPTO, ALBERT J. VAN NORSTRAND, JR.
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Publication number: 20170168823Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.Type: ApplicationFiled: December 11, 2015Publication date: June 15, 2017Inventors: SUNDEEP CHADHA, ROBERT A. CORDES, DAVID A. HRUSECKY, HUNG Q. LE, JENTJE LEENSTRA, DUNG Q. NGUYEN, BRIAN W. THOMPTO, ALBERT J. VAN NORSTRAND, JR.
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Patent number: 9519502Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines, a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, periodically check the image modification flags and write only the memory address of the flagged cache rows in the defined log. The processor unit is further arranged to monitor the free space available in the defined log and to trigger an interrupt if the free space available falls below a specific amount.Type: GrantFiled: November 20, 2014Date of Patent: December 13, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Guy L. Guthrie, Naresh Nayar, Geraint North, William J. Starke, Albert J. Van Norstrand, Jr.
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Publication number: 20150378770Abstract: A virtual machine backup method includes utilizing a log to indicate updates to memory of a virtual machine when the updates are evicted from a cache of the virtual machine. A guard band is determined that indicates a threshold amount of free space for the log. A determination is made that the guard band will be or has been encroached upon corresponding to indicating an update in the log. A backup image of the virtual machine is updated based, at least in part, on a set of one or more entries of the log, wherein the set of entries is sufficient to comply with the guard band. The set of entries is removed from the log.Type: ApplicationFiled: June 1, 2015Publication date: December 31, 2015Inventors: Guy L. Guthrie, Naresh Nayar, Geraint North, William J. Starke, Albert J. Van Norstrand, JR.
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Publication number: 20150143055Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines, a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, periodically check the image modification flags and write only the memory address of the flagged cache rows in the defined log. The processor unit is further arranged to monitor the free space available in the defined log and to trigger an interrupt if the free space available falls below a specific amount.Type: ApplicationFiled: November 20, 2014Publication date: May 21, 2015Inventors: Guy L. Guthrie, Naresh Nayar, Geraint North, William J. Starke, Albert J. Van Norstrand, JR.
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Patent number: 8200946Abstract: An issue unit for placing a processor into a gradual slow down mode of operation is provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.Type: GrantFiled: September 10, 2008Date of Patent: June 12, 2012Assignee: International Business Machines CorporationInventors: Christopher M. Abernathy, Kurt A. Feiste, Ronald P. Hall, Albert J. Van Norstrand, Jr.
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Patent number: 8131976Abstract: Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.Type: GrantFiled: April 13, 2009Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: Richard W. Doing, Susan E. Eisen, David S. Levitan, Kevin N. Magill, Brian R. Mestan, Balaram Sinharoy, Benjamin W. Stolt, Jeffrey R. Summers, Albert J. Van Norstrand, Jr.
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Patent number: 7818544Abstract: Mechanisms for placing a processor into a gradual slow down mode of operation are provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.Type: GrantFiled: September 5, 2008Date of Patent: October 19, 2010Assignee: International Business Machines CorporationInventors: Christopher M. Abernathy, Kurt A. Feiste, Ronald P. Hall, Albert J. Van Norstrand, Jr.
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Publication number: 20100262806Abstract: Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.Type: ApplicationFiled: April 13, 2009Publication date: October 14, 2010Applicant: International Business Machines CorporationInventors: Richard W. Doing, Susan E. Eisen, David S. Levitan, Kevin N. Magill, Brian R. Mestan, Balaram Sinharoy, Benjamin W. Stolt, Jeffrey R. Summers, Albert J. Van Norstrand, JR.
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Publication number: 20100262813Abstract: Mechanisms, in a processor, are provided for detecting and handling short forward branch conversion candidates. The mechanisms identify a conditional branch in the computer code and determine if the short forward conditional branch is to be converted to a non-branching conditional sequence of instructions. Moreover, the mechanisms convert the conditional branch to a non-branching conditional sequence of instructions comprising a resolve instruction and one or more conditional instructions dependent on the resolve instruction. In addition, the mechanisms execute the non-branching conditional sequence of instructions in place of the conditional branch in the computer code and generate an output of the computer code based on the execution of the non-branching conditional sequence of instructions.Type: ApplicationFiled: April 14, 2009Publication date: October 14, 2010Applicant: International Business Machines CorporationInventors: Mary D. Brown, Richard W. Doing, Kevin N. Magill, Brian R. Mestan, Wolfram M. Sauer, Balaram Sinharoy, Jeffrey R. Summers, Albert J. Van Norstrand, JR.
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Patent number: 7605612Abstract: A technique for clock gating a clock domain of an integrated circuit includes storing first, second, and third values in a control register. The first value corresponds to a first number of clock cycles to wait before initiating clock gating, the second value corresponds to a second number of clock cycles in which clock gating is performed, and the third value corresponds to a third number of clock cycles in which clock gating is not performed. One of the first, second, and third values is selectively loaded from the control register into a counting circuit. The counting circuit counts from the loaded one of the first, second, and third values to a transition value. A compare signal is received at the control state machine (from the counting circuit) that indicates the counting circuit has reached the transition value.Type: GrantFiled: May 16, 2008Date of Patent: October 20, 2009Assignee: International Business Machines CorporationInventors: Owen Chiang, Christopher M. Durham, Peter J. Klim, Daniel L. Stasiak, Albert J. Van Norstrand, Jr.
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Publication number: 20090006820Abstract: An issue unit for placing a processor into a gradual slow down mode of operation is provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.Type: ApplicationFiled: September 10, 2008Publication date: January 1, 2009Applicant: International Business Machines CorporationInventors: Christopher M. Abernathy, Kurt A. Feiste, Ronald P. Hall, Albert J. Van Norstrand, JR.
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Publication number: 20090006817Abstract: Mechanisms for placing a processor into a gradual slow down mode of operation are provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.Type: ApplicationFiled: September 5, 2008Publication date: January 1, 2009Applicant: International Business Machines CorporationInventors: Christopher M. Abernathy, Kurt A. Feiste, Ronald P. Hall, Albert J. Van Norstrand, JR.