Abstract: A processor and method of processing a multiple-register instruction are described. The processor includes execution circuitry and a set of registers, which are each capable of storing a data word. A multiple-register instruction specifying a plurality of data words that are to be written to a corresponding plurality of registers within the set of registers is dispatched to the execution circuitry. In response to receipt of the multiple-register instruction, the execution circuitry executes the multiple-register instruction, such that at least two data words among the plurality of data words are written to at least two corresponding registers among the plurality of registers during a single cycle of the processor.

Abstract: A method and system for executing a context-altering instruction within a processor are disclosed. The processor has a superscalar architecture that includes multiple pipelines, buffers, registers, and execution units. The processor also includes a machine state register for identifying a context of the processor, and a shadow machine state register in conjunction with the machine state register. During operation, a first state of the machine state register is copied to the shadow machine state register. Instructions are executed in accordance with a context identified by the first state of the machine state register. The first state of the shadow machine state register is subsequently altered to a second state in response to decoding a context-altering instruction. The context-altering instruction and subsequent instructions are then executed in accordance with the second state of the shadow machine state register.

Abstract: While a set-associative cache memory operates in a first power mode, information is stored in up to N number of ways of the cache memory, where N is an integer number and N>1. While the cache memory operates in a second power mode, the information is stored in up to M number of ways of the cache memory, where M is an integer number and 0<M<N.

Abstract: A system and method for improving arbitration of a plurality of events that may require access to a cache is disclosed. In a first aspect, the method and system provide dynamic arbitration. The first aspect comprises first logic for determining whether at least one of the plurality of events requires access to the cache and for outputting at least one signal in response thereto. Second logic coupled to the first logic determines the priority of each of the plurality of events in response to the at least one signal and outputs a second signal specifying the priority of each event. Third logic coupled to the second logic grants access to the cache in response to the second signal. A second aspect of the method and system provides user programmable arbitration. The second aspect comprises a storage unit which allows the user to input information indicating the priority of at least one of the plurality of events and outputs a first signal in response to the information.

Abstract: While dispatch circuitry operates in a first power mode, per cycle of the dispatch circuitry, up to N number of instructions are dispatched to execution circuitry for execution, where N is an integer number and N>1. While the dispatch circuitry operates in a second power mode, per cycle of the dispatch circuitry, up to M number of instructions are dispatched to the execution circuitry for execution, where M is an integer number and 0<M<N.

Abstract: A method for implementing a four-way least recently used cache line replacement scheme in a four-way cache memory is disclosed. The cache memory includes multiple cache lines, and each cache line includes four congruence sets. In accordance with the present disclosure, a 5-bit Least Recently Used (LRU) field is associated with each of the cache lines within the cache memory. For a particular cache line, a set number of a least recently used set among the four congruence sets is stored in any two bits of the LRU field associated with that cache line. Next, a set number of the second least recently used set among the four congruence sets is stored in another two bits of the same LRU field associated with the same cache line. Finally, a last bit of the 5-bit LRU field is set to a specific state in response to a determination of which one of the remaining two sets is the second most recently used set.

Abstract: A circular dispatch queue is used to implement an instruction queue, in a microprocessor, in order to reduce the delay associated with the critical timing path between an instruction cache memory and the instruction queue. In the circular dispatch queue, instructions are never moved from one stage to another. Instead, pointers are maintained that indicate the top and bottom instructions within the circular dispatch queue. This technique removes inputs from the multiplexor between the register stages in the circular dispatch queue and the instruction cache memory, thus reducing the critical delay.

Abstract: A processor and method for speculatively executing branch instructions utilizing a selected branch prediction methodology are disclosed. The processor has one or more execution units for executing instructions, including a branch processing unit for executing branch instructions. The branch processing unit includes selection logic for selecting one of a plurality of branch prediction methodologies and a branch prediction unit for predicting the resolution of a conditional branch instruction utilizing the selected branch prediction methodology. The branch processing unit further includes execution facilities for speculatively executing the conditional branch instruction based upon the prediction. Based upon the outcome of the prediction, the selection logic selects a branch prediction methodology for predicting a subsequent conditional branch instruction so that branch prediction accuracy is enhanced. In one embodiment, the multiple branch prediction methodologies include static and dynamic branch prediction.