Abstract: Provided is a distributed amplifier in communication systems, including: an input transmission line; an output transmission line; an input impedance match and an output impedance match, for providing termination of the input transmission line and the output transmission line, respectively and for preventing signal reflection in the input transmission line and the output transmission line, respectively; multi-stage Gm cells with common mode feedback, the input transmission line being coupled to the output transmission line by the transconductance of the Gm cells; and an input gate bias circuit, for providing bias for the multi-stage Gm cells. In at least one of the Gm cells, one inverter performs V/I conversion while other inverters provide negative resistance to control common mode of output voltage and to enhance DC gain of the Gm cell. Due to common mode feedback, no output gate bias is needed.

Abstract: Provided is a distributed amplifier in communication systems, including: an input transmission line; an output transmission line; an input impedance match and an output impedance match, for providing termination of the input transmission line and the output transmission line, respectively and for preventing signal reflection in the input transmission line and the output transmission line, respectively; multi-stage Gm cells with common mode feedback, the input transmission line being coupled to the output transmission line by the transconductance of the Gm cells; and an input gate bias circuit, for providing bias for the multi-stage Gm cells. In at least one of the Gm cells, one inverter performs V/I conversion while other inverters provide negative resistance to control common mode of output voltage and to enhance DC gain of the Gm cell. Due to common mode feedback, no output gate bias is needed.

Abstract: A layout of a power device is provided. The layout includes a substrate, a unit array, a plurality of first, second, third and fourth signal paths, and a first, second, third and fourth port. The unit array with a plurality of rows is disposed on the substrate. Each row of the unit array includes a plurality of units. The first and second signal paths on the substrate are disposed on a first side and a second side of corresponding odd-numbered rows of the unit array. The third and the fourth signal paths on the substrate are disposed above a corresponding row of the unit array. The first to fourth ports on the substrate are electrically connected to the first to fourth signal paths respectively.

Abstract: A layout of a power device is provided. The layout includes a substrate, a unit array, a plurality of first, second, third and fourth signal paths, and a first, second, third and fourth port. The unit array with a plurality of rows is disposed on the substrate. Each row of the unit array includes a plurality of units. The first and second signal paths on the substrate are disposed on a first side and a second side of corresponding odd-numbered rows of the unit array. The third and the fourth signal paths on the substrate are disposed above a corresponding row of the unit array. The first to fourth ports on the substrate are electrically connected to the first to fourth signal paths respectively.

Abstract: The invention is directed to a method for manufacturing a metal-insulator-metal transformer together with a capacitor. The method comprises steps of providing a substrate having at least a dielectric layer formed thereon and then forming a first metal layer of the metal-insulator-metal capacitor together with a first metal coil of the transformer over the substrate. An insulating layer is formed to cover the substrate, the first metal layer and the first metal coil. A second metal layer of the metal-insulator-metal capacitor is formed together with a second metal coil of the transformer on the insulating layer.

Abstract: A radio frequency (RF) integrated circuit with electrostatic discharge (ESD) protection and an ESD protection apparatus thereof are provided. The ESD protection apparatus includes a substrate, an RF bonding pad, and an ESD protection unit. The RF bonding pad for transmitting RF signal is disposed upon the substrate. The ESD protection unit is disposed under the RF bonding pad. Wherein, The ESD protection unit includes an inductor electrically connected between the RF bonding pad and the power rail.

Abstract: A transmit-receive switch for ultrawideband and a method for isolating transmitting and receiving signal thereof are provided. The transmit-receive switch includes a first switch, a second switch, and an inductor. The first switch has a first end coupled to a signal transmitting end, a second end coupled to a signal transmit-receive end, and a control end receiving a first control signal to decide whether or not to turn on the first switch according to the first controlling signal. The second switch has a first end coupled to a signal receiving end, a second end coupled to the signal transmit-receive end, and a control end receiving a second control signal to decide whether or not to turn on the second switch according to the second controlling signal. The inductor has an end coupled to the signal transmit-receive end, and another end coupled to a first potential.

Abstract: The invention is directed to a method for manufacturing a metal-insulator-metal transformer together with a capacitor. The method comprises steps of providing a substrate having at least a dielectric layer formed thereon and then forming a first metal layer of the metal-insulator-metal capacitor together with a first metal coil of the transformer over the substrate. An insulating layer is formed to cover the substrate, the first metal layer and the first metal coil. A second metal layer of the metal-insulator-metal capacitor is formed together with a second metal coil of the transformer on the insulating layer.

Abstract: A capacitor structure is described, including a first capacitor and a second capacitor. The first capacitor includes a first electrode, a second electrode and a first insulating layer, wherein the second electrode is disposed under the first electrode and the first insulating layer between the first electrode and the second electrode. The second capacitor is disposed under the first capacitor and coupled thereto in parallel. The second capacitor includes multiple patterned metal layers and via plugs that constitute a third electrode and a fourth electrode, and a second insulating layer. The patterned metal layers are stacked in the second insulating layer and connected by the via plugs, wherein each patterned metal layer includes a portion of the third electrode and a portion of the fourth electrode that are separated by the second insulating layer.