Patents by Inventor Albert Meixner

Albert Meixner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11481884
    Abstract: Techniques for image quality enhancement for autonomous vehicle remote operations are disclosed herein. An image processing system of an autonomous vehicle can obtain images captured by at least two different cameras and stitch the images together to create a combined image. The image processing system can apply region blurring to a portion of the combined image to create an enhanced combined image, e.g., to blur regions/objects determined to be less import (or unimportant) for the remote operations. The image processing system can encode pixel areas of the enhanced combined image using a corresponding quality setting for respective pixel areas to create encoded image files, e.g., based on complexity levels of the respective pixel areas. The image processing system can transmit the encoded image files to a remote operations system associated with the autonomous vehicle for remote operations support.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: October 25, 2022
    Assignee: NURO, INC.
    Inventors: Yichao (Roger) Shen, Alexandr Bakhturin, Chenjie Luo, Albert Meixner, Ian Zhou, Hubert Hua Kian Teo, William Paul Maddern
  • Publication number: 20220206796
    Abstract: An apparatus is described that includes an execution unit having a multiply add computation unit, a first ALU logic unit and a second ALU logic unit. The ALU unit is to perform first, second, third and fourth instructions. The first instruction is a multiply add instruction. The second instruction is to perform parallel ALU operations with the first and second ALU logic units operating simultaneously to produce different respective output resultants of the second instruction. The third instruction is to perform sequential ALU operations with one of the ALU logic units operating from an output of the other of the ALU logic units to determine an output resultant of the third instruction. The fourth instruction is to perform an iterative divide operation in which the first ALU logic unit and the second ALU logic unit operate during to determine first and second division resultant digit values.
    Type: Application
    Filed: March 10, 2022
    Publication date: June 30, 2022
    Inventors: Artem Vasilyev, Jason Rupert Redgrave, Albert Meixner, Ofer Shacham
  • Patent number: 11321802
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for supporting large lookup tables on an image processor. One of the methods includes receiving an input kernel program for an image processor having a two-dimensional array of execution lanes, a shift-register array, and a plurality of memory banks. If the kernel program has an instruction that reads a lookup table value for a lookup table partitioned across the plurality of memory banks, the instruction in the kernel program are replaced with a sequence of instructions that, when executed by an execution lane, causes the execution lane to read a first value from a local memory bank and a second value from the local memory bank on behalf of another execution lane belonging to a different group of execution lanes.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: May 3, 2022
    Assignee: Google LLC
    Inventors: Albert Meixner, Dustin Michael DeWeese
  • Patent number: 11250537
    Abstract: An image processor unit is described. The image processor unit includes a plurality of inputs to receive at least one input image. The image processor unit includes a plurality of outputs to provide at least one output image. The image processor unit includes a network coupled to the plurality of inputs and the plurality of outputs. The network is to couple at least one of the inputs to at least one of the outputs. The image processor unit includes an image processor circuit coupled to the network. The network to route an input image that is received at one of the inputs to the image processor circuit. The image processor circuit is to execute image signal processing program code to generate a processed output image from the input image. The network is to route the processed output image to at least one of the outputs.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: February 15, 2022
    Assignee: Google LLC
    Inventors: Fabrizio Basso, Edward Chang, Daniel Finchelstein, Timothy Knight, William Mark, Albert Meixner, Shahriar Rabii, Jason Redgrave, Masumi Reynders, Ofer Shacham, Don Stark, Michelle Tomasko
  • Publication number: 20210383517
    Abstract: Techniques for image quality enhancement for autonomous vehicle remote operations are disclosed herein. An image processing system of an autonomous vehicle can obtain images captured by at least two different cameras and stitch the images together to create a combined image. The image processing system can apply region blurring to a portion of the combined image to create an enhanced combined image, e.g., to blur regions/objects determined to be less import (or unimportant) for the remote operations. The image processing system can encode pixel areas of the enhanced combined image using a corresponding quality setting for respective pixel areas to create encoded image files, e.g., based on complexity levels of the respective pixel areas. The image processing system can transmit the encoded image files to a remote operations system associated with the autonomous vehicle for remote operations support.
    Type: Application
    Filed: February 11, 2021
    Publication date: December 9, 2021
    Inventors: Yichao (Roger) SHEN, Alexandr BAKHTURIN, Chenjie LUO, Albert MEIXNER, Ian ZHOU, Hubert Hua Kian TEO, William Paul MADDERN
  • Patent number: 11196953
    Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: December 7, 2021
    Assignee: Google LLC
    Inventors: Albert Meixner, Daniel Frederic Finchelstein, David Patterson, William R. Mark, Jason Rupert Redgrave, Ofer Shacham
  • Patent number: 11190718
    Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: November 30, 2021
    Assignee: Google LLC
    Inventors: Neeti Desai, Albert Meixner, Qiuling Zhu, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein
  • Patent number: 11182138
    Abstract: A method is described that includes translating higher level program code including higher level instructions having an instruction format that identifies pixels to be accessed from a memory with first and second coordinates from an orthogonal coordinate system into lower level instructions that target a hardware architecture having an array of execution lanes and a shift register array structure that is able to shift data along two different axis. The translating includes replacing the higher level instructions having the instruction format with lower level shift instructions that shift data within the shift register array structure.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: November 23, 2021
    Assignee: Google LLC
    Inventor: Albert Meixner
  • Patent number: 11153464
    Abstract: An apparatus is described. The apparatus includes an execution lane array coupled to a two dimensional shift register array structure. Locations in the execution lane array are coupled to same locations in the two-dimensional shift register array structure such that different execution lanes have different dedicated registers.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: October 19, 2021
    Assignee: Google LLC
    Inventors: Ofer Shacham, Jason Rupert Redgrave, Albert Meixner, Qiuling Zhu, Daniel Frederic Finchelstein, David Patterson, Donald Stark
  • Patent number: 11138013
    Abstract: An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: October 5, 2021
    Assignee: Google LLC
    Inventors: Albert Meixner, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein, Qiuling Zhu
  • Patent number: 11140293
    Abstract: A sheet generator circuit is described. The sheet generator includes electronic circuitry to receive a line group of image data including multiple rows of data from a frame of image data. The multiple rows are sufficient in number to encompass multiple neighboring overlapping stencils. The electronic circuitry is to parse the line group into a smaller sized sheet. The electronic circuitry is to load the sheet into a data computation unit having a two dimensional shift array structure coupled to an array of processors.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: October 5, 2021
    Assignee: Google LLC
    Inventors: Albert Meixner, Jason Rupert Redgrave, Ofer Shacham, Qiuling Zhu, Daniel Frederic Finchelstein
  • Publication number: 20210255972
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for a system-level cache to allocate cache resources by a way-partitioning process. One of the methods includes maintaining a mapping between partitions and priority levels and allocating primary ways to respective enabled partitions in an order corresponding to the respective priority levels assigned to the enabled partitions.
    Type: Application
    Filed: December 31, 2020
    Publication date: August 19, 2021
    Inventors: Vinod Chamarty, Xiaoyu Ma, Hongil Yoon, Keith Robert Pflederer, Weiping Liao, Benjamin Dodge, Albert Meixner, Allan Douglas Knies, Manu Gulati, Rahul Jagdish Thakur, Jason Rupert Redgrave
  • Patent number: 11030005
    Abstract: A method is described. The method includes calculating data transfer metrics for kernel-to-kernel connections of a program having a plurality of kernels that is to execute on an image processor. The image processor includes a plurality of processing cores and a network connecting the plurality of processing cores. Each of the kernel-to-kernel connections include a producing kernel that is to execute on one of the processing cores and a consuming kernel that is to execute on another one of the processing cores. The consuming kernel is to operate on data generated by the producing kernel. The method also includes assigning kernels of the plurality of kernels to respective ones of the processing cores based on the calculated data transfer metrics.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: June 8, 2021
    Assignee: Google LLC
    Inventors: Hyunchul Park, Albert Meixner
  • Publication number: 20210165656
    Abstract: An image processor is described. The image processor includes a two dimensional shift register array that couples certain ones of its array locations to support execution of a shift instruction. The shift instruction is to include mask information. The mask information is to specify which of the array locations are to be written to with information being shifted. The two dimensional shift register array includes masking logic circuitry to write the information being shifted into specified ones of the array locations in accordance with the mask information.
    Type: Application
    Filed: February 8, 2021
    Publication date: June 3, 2021
    Inventor: Albert Meixner
  • Patent number: 10996988
    Abstract: A method is described. The method includes constructing an image processing software data flow in which a buffer stores and forwards image data being transferred from a producing kernel to one or more consuming kernels. The method also includes recognizing that the buffer has insufficient resources to store and forward the image data. The method also includes modifying the image processing software data flow to include multiple buffers that store and forward the image data during the transfer of the image data from the producing kernel to the one or more consuming kernels.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: May 4, 2021
    Assignee: Google LLC
    Inventors: Hyunchul Park, Albert Meixner
  • Publication number: 20210042875
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for supporting large lookup tables on an image processor. One of the methods includes receiving an input kernel program for an image processor having a two-dimensional array of execution lanes, a shift-register array, and a plurality of memory banks. If the kernel program has an instruction that reads a lookup table value for a lookup table partitioned across the plurality of memory banks, the instruction in the kernel program are replaced with a sequence of instructions that, when executed by an execution lane, causes the execution lane to read a first value from a local memory bank and a second value from the local memory bank on behalf of another execution lane belonging to a different group of execution lanes.
    Type: Application
    Filed: February 21, 2019
    Publication date: February 11, 2021
    Inventors: Albert Meixner, Dustin Michael DeWeese
  • Patent number: 10915773
    Abstract: A method is described that includes loading an array of content into a two-dimensional shift register. The two-dimensional shift register is coupled to an execution lane array. The method includes repeatedly performing a first sequence including: shifting with the shift register first content residing along a particular row or column into another parallel row or column where second content resides and performing operations with a particular corresponding row or column of the execution lane array on the first and second content. The method also includes repeatedly performing a second sequence including: shifting with the shift register content from a set of first locations along a resultant row or column that is parallel with the rows or columns of the first sequence into a corresponding set of second locations along the resultant row or column. The resultant row or column has values determined from the operations of the first sequence.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: February 9, 2021
    Assignee: Google LLC
    Inventors: Edward Chang, Daniel Frederic Finchelstein, Szepo Robert Hung, Albert Meixner, Ofer Shacham
  • Patent number: 10915319
    Abstract: An image processor is described. The image processor includes a two dimensional shift register array that couples certain ones of its array locations to support execution of a shift instruction. The shift instruction is to include mask information. The mask information is to specify which of the array locations are to be written to with information being shifted. The two dimensional shift register array includes masking logic circuitry to write the information being shifted into specified ones of the array locations in accordance with the mask information.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: February 9, 2021
    Assignee: Google LLC
    Inventor: Albert Meixner
  • Publication number: 20210004633
    Abstract: A method is described that includes executing a convolutional neural network layer on an image processor having an array of execution lanes and a two-dimensional shift register. The two-dimensional shift register provides local respective register space for the execution lanes. The executing of the convolutional neural network includes loading a plane of image data of a three-dimensional block of image data into the two-dimensional shift register.
    Type: Application
    Filed: September 22, 2020
    Publication date: January 7, 2021
    Inventors: Ofer Shacham, David Patterson, William R. Mark, Albert Meixner, Daniel Frederic Finchelstein, Jason Rupert Redgrave
  • Publication number: 20210004232
    Abstract: An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.
    Type: Application
    Filed: August 24, 2020
    Publication date: January 7, 2021
    Inventors: Albert Meixner, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein, Qiuling Zhu