Patents by Inventor Albert R. Boothroyd

Albert R. Boothroyd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Optical waveguide and method for its manufacture
    Patent number: 5035916
    Abstract: An optical waveguide is made by forming a layer of SiO.sub.2 on a substrate and implanting a region of the SiO.sub.2 layer with Si ions to define a region containing a stoichiometric excess of Si which defines a region having an elevated refractive index surrounded by a region having a lower refractive index. The resulting optical waveguide is stable at the high temperatures required for many semiconductor processing methods, and is useful for optical interconnection in integrated optical and optoelectronic devices.
    Type: Grant
    Filed: March 28, 1990
    Date of Patent: July 30, 1991
    Assignee: Northern Telecom Limited
    Inventors: Alexander Kalnitsky, Joseph P. Ellul, Albert R. Boothroyd
  • Optical waveguide and method for its manufacture
    Patent number: 4934774
    Abstract: An optical waveguide is made by forming a layer of SiO.sub.2 on a substrate and implanting a region of the SiO.sub.2 layer with Si ions to define a region containing a stoichiometric excess of Si which defines a region having an elevated refractive index surrounded by a region having a lower refractive index. The resulting optical waveguide is stable at the high temperatures required for many semiconductor processing methods, and is useful for optical interconnection in integrated optical and optoelectronic devices.
    Type: Grant
    Filed: June 8, 1989
    Date of Patent: June 19, 1990
    Assignee: Northern Telecom Limited
    Inventors: Alexander Kalnitsky, Joseph P. Ellul, Albert R. Boothroyd
  • Stacked MOS transistor
    Patent number: 4476475
    Abstract: In a stacked metal-oxide-semiconductor (SMOS) transistor, the transistor source, drain and channel each have a lower part formed in a silicon substrate and an upper part composed of recrystallized polysilicon. The device gate is located between the upper and lower channel parts. By vertically integrating a MOS transistor, performance limitations imposed by the direct scaling approach to device miniaturization are avoided.
    Type: Grant
    Filed: November 19, 1982
    Date of Patent: October 9, 1984
    Assignee: Northern Telecom Limited
    Inventors: Abdalla A. Naem, Hussein M. Naguib, Iain D. Calder, Albert R. Boothroyd