Abstract: Briefly, in accordance with one embodiment of the invention, a system includes two boards coupled by a bus. The bus having a dual-terminated transmission line that communicatively couples a memory control hub with a memory repeater hub that each have a Rambus ASIC Cell (RAC). Briefly, in accordance with another embodiment of the invention, a connector has two metal traces that are of different lengths. The parasitic capacitance of the longer metal trace is increased so that the impedance of the two metal traces is substantially equal.

Abstract: Flexible control of access to a Basic Input/Output System memory is provided by a programmable non-volatile storage unit that stores a non-volatile signal and generates a control signal based on the non-volatile signal. A control circuit coupled to the programmable non-volatile storage unit receives the control signal from the non-volatile storage unit. The control circuit also receives a BIOS memory address signal and generates a modified BIOS memory address signal. In this way, different BIOS programs may be accessed on boot-up.

Abstract: An interrupt handling mechanism for converting PCI agent interrupts into interrupts compliant with a secondary bus standard interrupt protocol. PCI agent interrupts are processed by programmable logic for converting PCI compliant interrupts into, for example, ISA bus standard compliant interrupts for processing by a computer system which implements both a PCI bus and ISA bus. A programmable register provides for selecting which ISA interrupt will be generated by the programmable logic in response to a PCI agent interrupt.

Abstract: An interconnect mechanism for allowing use of an IDE compatible add-in card in a PCI compliant expansion slot. Unused PCI pins are exploited to provide for proper routing of necessary interrupt signals from an IDE add-in card. The presence of the IDE card in the PCI slot enables signaling circuitry for routing IDE interrupts to the computer system's interrupt controller and reroutes existing hard disk interrupt signals to the interrupt controller as a secondary hard disk interrupt. Another otherwise unused pin is exploited to provide a signal for lighting the computer system's hard disk active indicating LED. The gating circuitry is provided such that non-IDE, PCI-compliant add-in cards are provided with unaffected operation in the PCI slot.