Abstract: Described herein are novel PRMT5 inhibitors of Formula I and pharmaceutically acceptable salts thereof, as well as the pharmaceutical compositions thereof. Compounds of the present invention are useful for inhibiting PRMT5 activity and may have use in treating proliferative, metabolic and blood disorders.

Abstract: Described herein are compounds of Formula (I) and pharmaceutically acceptable salts thereof, as well as pharmaceutical compositions thereof. Compounds of the present invention are useful for inhibiting PRMT5 activity and may have use in treating proliferative, such as cancer, metabolic and blood disorders. Compounds of Formula (I) have the following structure of Formula (I).

Abstract: A source processing node communicates with a destination processing node though a channel that has bandwidth requirements and is uni-directional. The source processing node generates the channel to the destination processing node. The destination processing node then accepts the channel. The source processing node allocates a transmit buffer for the channel. The destination processing node also allocates a receive buffer for the channel. A source processing element writes data to the transmit buffer for the channel. A source network interface transmits the data from the transmit buffer of the source processing node over the channel. A destination network interface receives the data into the receive buffer for the channel. A destination processing element receives the data from the receive buffer.

Abstract: A processing system with reconfigurable instruction extensions includes a processor, programmable logic, a register file, and a load/store module. The processor executes a computer program comprising a set of computational instructions and at least one instruction extension. The programmable logic receives configuration information to configure the programmable logic for the instruction extension and executes the instruction extension. The register file is coupled to the programmable logic and stores data. The load/store module transfers the data directly between the register file and a system memory.

Abstract: An integrated circuit with selectable input/output includes a first processor configured to execute instructions, an input/output interface configured to receive and transmit standard input/output communications, an inter-processor interface configured to process interprocessor communications with a second processor, and selection circuitry coupled to both the input/output interface and the inter-processor interface and configured to select between the input/output interface and the inter-processor interface.

Abstract: A processing system with reconfigurable instruction extensions includes a processor, programmable logic, a register file, and a load/store module. The processor executes a computer program comprising a set of computational instructions and at least one instruction extension. The programmable logic receives configuration information to configure the programmable logic for the instruction extension and executes the instruction extension. The register file is coupled to the programmable logic and stores data. The load/store module transfers the data directly between the register file and a system memory.

Abstract: A system for processing applications includes processor nodes and links interconnecting the processor nodes. Each node includes a processing element, a software extensible device, and a communication interface. The processing element executes at least one of the applications. The software extensible device provides additional instructions to a set of standard instructions for the processing element. The communication interface communicates with other processor nodes.

Abstract: A system for adding advanced instructions to a microprocessor includes a language for formally capturing the new instructions and a method for generating hardware implementations and software tools for the extended processors. The extension language provides for additions of VLIW instructions, complex load/store instructions, more powerful description styles using functions, more powerful register operands, and a new set of built-in modules. The method is capable of generating fully-pipelined micro-architectural implementations for the new instructions in the form of synthesizable HDL descriptions which can be processed by standard CAD tools. The method is also capable of generating software components for extending software development tools for the microprocessor with new instructions.

Abstract: A video processing system with reconfigurable instructions includes a processor, a first register file in the processor, an extension adapter, programmable logic, a second register file coupled to the programmable logic, and a load/store module. The processor executes a video application that contains an instruction extension not native to the instruction set of the processor. The extension adapter detects the instruction extension in the video application. The programmable logic device is configured to execute the instruction extension. The programmable logic device then executes the instruction extension. The load/store module transfers data between the first register file and the second register file, and transfers data directly between the second register file and a system memory for use by the processor in processing the video application.

Abstract: A system and method for adding reconfigurable computational instructions to a reduced instruction set computer. A computer program contains instruction extensions not native to the instruction set of the processor core and is loaded into an instruction memory accessible by the processor core of the computer. The computer program is then detected for containing the instruction extension. The programmable logic device is then configured to execute the instruction extension. The programmable logic device then executes the instruction extension for use by the processor core in processing the computer program.

Abstract: A system for processing applications includes processor nodes and links interconnecting the processor nodes. Each node includes a processing element, a software extensible device, and a communication interface. The processing element executes at least one of the applications. The software extensible device provides additional instructions to a set of standard instructions for the processing element. The communication interface communicates with other processor nodes.

Abstract: A universal synchronization element is used in a static timing verification system to represent selected combinational primitive elements, synchronous primitive elements and external primitive elements in the user's synchronous digital circuit. Each of these digital circuit element in a user's digital circuit design is represented by a corresponding universal synchronization element having a propagation time characteristic equivalent to the digital circuit element and a stable time characteristic equivalent to the digital circuit element. The propagation and stable time characteristics are defined in relation to a clock signal for the digital circuit element in the user's circuit that the universal synchronization element represents. The universal synchronization element does not a fixed timing relationship between the signals on its input and output terminals.

Abstract: A new method and structure are provided for simulating the time delay associated with signal propagation through a mapped and optimized logic network for a selected target technology using only information from an unmapped logic network. For each target technology, the method and structure include the time delay characteristics of the mapping and optimization strategies used to generate an optimized network using the library of standard gates for that target technology. The functional complexity of each unmapped logic node and the complexity of the fanout for each unmapped logic node are also included in the simulated time delay.