Abstract: Embodiments of the present invention are directed to parallel, pipelined, integrated-circuit implementations of computational engines designed to solve complex computational problems. One embodiment of the present invention is a family of video encoders and decoders (“codecs”) that can be incorporated within cameras, cell phones, and other electronic devices for encoding raw video signals into compressed video signals for storage and transmission, and for decoding compressed video signals into raw video signals for output to display devices. A highly parallel, pipelined, special-purpose integrated-circuit implementation of a particular video codec provides, according to embodiments of the present invention, a cost-effective video-codec computational engine that provides an extremely large computational bandwidth with relatively low power consumption and low-latency for decompression and compression of compressed video signals and raw video signals, respectively.

Abstract: An electromagnetic connector is disclosed that is configured to form a first magnetic circuit portion comprising multiple coils disposed about a first core member. The electromagnetic connector is configured to mate with a second electromagnetic connector that is configured to form a second magnetic circuit portion comprising a coil disposed about a second core member. When the electromagnetic connector is mated with the second electromagnetic connector, the first core member and the second core member are configured to couple the multiple coils of the electromagnetic connector to the coil of the second electromagnetic connector with a magnetic circuit formed from the first magnetic circuit portion and the second magnetic circuit portion. The magnetic circuit is configured to induce a signal in a first coil of the multiple coils and the coil of the second electromagnetic connector when a second coil of the multiple coils is energized.

Abstract: An electromagnetic connector well suited for use in harsh environments. The connector used an E-core or C-core magnetic members for coupling power such as from a backplane to a module mounted on the backplane and using I-cores for coupling signals to and from the module. Separation of the power and signaling allows optimization of each coupling without compromise in performance of each function. Use of I-cores for signal coupling provides efficient use of space, with the use of E-cores or C-cores providing maximum power coupling to the module in a minimum space. Various aspects of exemplary embodiments are disclosed.

Abstract: A communications control system is disclosed that includes a serial communications interface and a parallel communications interface for coupling a plurality of input/output modules with a control module. The serial communications interface is configured for connecting the plurality of input/output modules to the control module in parallel to transmit information between the plurality of input/output modules and the control module, and the parallel communications interface is configured for separately connecting the plurality of input/output modules to the control module to transmit information between the plurality of input/output modules and the control module, and to transmit information between individual ones of the plurality of input/output modules. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.

Abstract: A switch fabric is disclosed that includes a serial communications interface and a parallel communications interface. The serial communications interface is configured for connecting a plurality of slave devices to a master device in parallel to transmit information between the plurality of slave devices and the master device, and the parallel communications interface is configured for separately connecting the plurality of slave devices to the master device to transmit information between the plurality of slave devices and the master device, and to transmit information between individual ones of the plurality of slave devices. The parallel communications interface may comprise a dedicated parallel communications channel for each one of the plurality of slave devices. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.

Abstract: Embodiments of the present invention are directed to parallel, pipelined, integrated-circuit implementations of computational engines designed to solve complex computational problems. One embodiment of the present invention is a family of video encoders and decoders (“codecs”) that can be incorporated within cameras, cell phones, and other electronic devices for encoding raw video signals into compressed video signals for storage and transmission, and for decoding compressed video signals into raw video signals for output to display devices. A highly parallel, pipelined, special-purpose integrated-circuit implementation of a particular video codec provides, according to embodiments of the present invention, a cost-effective video-codec computational engine that provides an extremely large computational bandwidth with relatively low power consumption and low-latency for decompression and compression of compressed video signals and raw video signals, respectively.

Abstract: Embodiments of the present invention are directed to memory subsystems implemented within, or connected to and accessed by, parallel, pipelined, integrated-circuit implementations of computational engines designed to solve complex computational problems. Additional embodiments of the present invention are directed to memory subsystems implemented within, or connected to and accessed by, a variety of different types of electronic devices. One embodiment of the present invention comprises a memory controller implemented in a first integrated circuit or other electronic system and one or more separate memory devices. Alternative embodiments of the present invention incorporate the memory controller within one or more memory devices that are connected to, and accessed by, an integrated-circuit-implemented computational engine or another electronic device.

Abstract: Embodiments of the present invention relate to a multi-bus architecture within a video codec that discretely and efficiently transports video components within the codec. This multi-bus architecture provides a relatively more efficient transport mechanism because the various buses are designed to specifically address unique characteristics of the video components or parameters being processed within the codec.

Abstract: A communications control system is disclosed that includes a serial communications interface and a parallel communications interface for coupling a plurality of input/output modules with a control module. The serial communications interface is configured for connecting the plurality of input/output modules to the control module in parallel to transmit information between the plurality of input/output modules and the control module, and the parallel communications interface is configured for separately connecting the plurality of input/output modules to the control module to transmit information between the plurality of input/output modules and the control module, and to transmit information between individual ones of the plurality of input/output modules. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.

Abstract: An electromagnetic connector is disclosed that is configured to form a first magnetic circuit portion comprising a first core member and a first coil disposed of the first core member. The electromagnetic connector is configured to mate with a second electromagnetic connector, where the second electromagnetic connector is configured to form a second magnetic circuit portion comprising a second core member and a second coil disposed of the second core member. The first core member and the second core member are configured to couple the first coil to the second coil with a magnetic circuit formed from the first magnetic circuit portion and the second magnetic circuit portion when the electromagnetic connector is mated with the second electromagnetic connector. The magnetic circuit is configured to induce a signal in the first coil when the second coil is energized.

Abstract: A switch fabric is disclosed that includes a serial communications interface and a parallel communications interface. The serial communications interface is configured for connecting a plurality of slave devices to a master device in parallel to transmit information between the plurality of slave devices and the master device, and the parallel communications interface is configured for separately connecting the plurality of slave devices to the master device to transmit information between the plurality of slave devices and the master device, and to transmit information between individual ones of the plurality of slave devices. The parallel communications interface may comprise a dedicated parallel communications channel for each one of the plurality of slave devices. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.

Abstract: Embodiments of the present invention relate to a multi-bus architecture within a video codec that discretely and efficiently transports video components within the codec. This multi-bus architecture provides a relatively more efficient transport mechanism because the various buses are designed to specifically address unique characteristics of the video components or parameters being processed within the codec.

Abstract: Embodiments of the present invention are video acquisition and processing systems. One embodiment of the present invention, video acquisition and processing systems include a sensor, image signal processor, and video compression and decompression components fully integrated in a single integrated circuit. The integrated sensor and image signal processor feature highly parallel transmission of image data to the video compression and decompression component. This highly parallel, pipelined, special-purpose integrated-circuit implementation offers cost-effective video acquisition and image data processing and an extremely large computational bandwidth with relatively low power consumption and low-latency for processing video signals.

Abstract: Embodiments of the present invention are directed to parallel, pipelined, integrated-circuit implementations of computational engines designed to solve complex computational problems. One embodiment of the present invention is a family of video encoders and decoders (“codecs”) that can be incorporated within cameras, cell phones, and other electronic devices for encoding raw video signals into compressed video signals for storage and transmission, and for decoding compressed video signals into raw video signals for output to display devices. A highly parallel, pipelined, special-purpose integrated-circuit implementation of a particular video codec provides, according to embodiments of the present invention, a cost-effective video-codec computational engine that provides an extremely large computational bandwidth with relatively low power consumption and low-latency for decompression and compression of compressed video signals and raw video signals, respectively.

Abstract: Embodiments of the present invention are directed to memory subsystems implemented within, or connected to and accessed by, parallel, pipelined, integrated-circuit implementations of computational engines designed to solve complex computational problems. Additional embodiments of the present invention are directed to memory subsystems implemented within, or connected to and accessed by, a variety of different types of electronic devices. One embodiment of the present invention comprises a memory controller implemented in a first integrated circuit or other electronic system and one or more separate memory devices. Alternative embodiments of the present invention incorporate the memory controller within one or more memory devices that are connected to, and accessed by, an integrated-circuit-implemented computational engine or another electronic device.

Abstract: An operator workstation has a worksurface and left and right upper support members extending upward from the worksurface. Multiple flat-panel display units are mounted between the support members above the level of the worksurface. The displays are mounted above one another, between the support members. Lower support members support the workstation in connection with a base mounted between the lower support members. The base has a substantially triangular cross-section, while the lower support members have a substantially triangular shape.

Abstract: An operator workstation has a worksurface and left and right upper support members extending upward from the worksurface. Multiple flat-panel display units are mounted between the support members above the level of the worksurface. The displays are mounted above one another, between the support members. Lower support members support the workstation in connection with a base mounted between the lower support members. The base has a substantially triangular cross-section, while the lower support members have a substantially triangular shape.

Abstract: Equipment storage apparatus, such as equipment racks and cabinets, according to the invention have a vertical load bearing member with a stepped cross-section. Thus, for example, a load bearing member of a frame according to one aspect of the invention can have two faces on its front: one with a frontward directed normal for accommodating equipment mounts, and one with a frontward directed normal for accommodating front door mounts. A pair of such load bearing members can be provided, along with one or more horizontal cross-pieces or other such structural elements, to form a frame defining a generally rectangular central region in which mounted equipment is disposed.

Abstract: An operator workstation has a worksurface and left and right upper support members extending upward from the worksurface. Multiple flat-panel display units are mounted between the support members above the level of the worksurface. The displays are mounted above one another, between the support members. Lower support members support the workstation in connection with a base mounted between the lower support members. The base has a substantially triangular cross-section, while the lower support members have a substantially triangular shape.