Patents by Inventor ALBERT S. CHENG

ALBERT S. CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240097346
    Abstract: Methods for constructing multi-walled carbon nanotube (MWCNT) antenna arrays, may include: variable doping of the MWCNTs, forming light pipes with layers of variable dielectric glass, forming geometric diodes on full-wave rectified devices that propagate both electrons and holes, using clear conductive ground plans to form windows that can control a building's internal temperature, and generating multiple lithographic patterns with a single mask.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 21, 2024
    Inventors: Laurence H. COOKE, Darin S. OLSON, Paul COMITA, Robert E. COUSINS, Albert K. HENNING, Andreas HEGEDUS, David B. COOKE, Yao Te CHENG, John BURKE, Richard T. PRESTON
  • Patent number: 11528229
    Abstract: This disclosure describes systems, devices, methods and computer readable media for enhanced network communication for use in higher performance applications including storage, high performance computing (HPC) and Ethernet-based fabric interconnects. In some embodiments, a network controller may include a transmitter circuit configured to transmit packets on a plurality of virtual lanes (VLs), the VLs associated with a defined VL priority and an allocated share of network bandwidth. The network controller may also include a bandwidth monitor module configured to measure bandwidth consumed by the packets and an arbiter module configured to adjust the VL priority based on a comparison of the measured bandwidth to the allocated share of network bandwidth. The transmitter circuit may be further configured to transmit the packets based on the adjusted VL priority.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: December 13, 2022
    Assignee: Intel Corporation
    Inventors: Albert S. Cheng, Thomas D. Lovett, Michael A. Parker
  • Patent number: 11055247
    Abstract: In some embodiments, the invention involves using a weighted arbiter switch to provide fairness in passing input streams through a plurality of input ports to an output port. The weighted arbiter switches may be combined in a hierarchical architecture to enable routing through many levels of switches. Each input port has an associated flow counter to count input stream traffic through the input port. An arbiter switch uses the flow counts and weights from arbiter switches at a lower level in the hierarchy to generate a fairly distributed routing of input streams through the output port. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Gaspar Mora Porta, Michael A Parker, Roberto Penaranda Cebrian, Albert S Cheng, Francesc Guim Bernat
  • Patent number: 10951526
    Abstract: Technologies for determining a root of congestion include a network switch. The network switch is to operate arbiter units in at least one upstream stage at a packet transfer rate that is greater than a packet transfer rate of an arbiter unit in an output stage, determine whether an input buffer of a remote network switch in communication with the output stage has sustained congestion over a first predefined time period, determine whether an output buffer of the arbiter unit in the output stage has sustained congestion over a second predefined time period, and determine, as a function of whether the input buffer of the remote network switch has sustained congestion and whether the output buffer of the arbiter unit in the output stage has sustained congestion, whether the network switch is a root of congestion.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Albert S. Cheng, Michael A. Parker
  • Publication number: 20210036959
    Abstract: This disclosure describes systems, devices, methods and computer readable media for enhanced network communication for use in higher performance applications including storage, high performance computing (HPC) and Ethernet-based fabric interconnects. In some embodiments, a network controller may include a transmitter circuit configured to transmit packets on a plurality of virtual lanes (VLs), the VLs associated with a defined VL priority and an allocated share of network bandwidth. The network controller may also include a bandwidth monitor module configured to measure bandwidth consumed by the packets and an arbiter module configured to adjust the VL priority based on a comparison of the measured bandwidth to the allocated share of network bandwidth. The transmitter circuit may be further configured to transmit the packets based on the adjusted VL priority.
    Type: Application
    Filed: July 14, 2020
    Publication date: February 4, 2021
    Applicant: Intel Corporation
    Inventors: ALBERT S. CHENG, THOMAS D. LOVETT, MICHAEL A. PARKER
  • Patent number: 10911366
    Abstract: Technologies for balancing throughput across input ports include a network switch. The network switch is to generate, for an arbiter unit in a first stage of a hierarchy of stages of arbiter units, turn data indicative of a set of turns in which to transfer packet data from devices connected to input ports of the arbiter unit. The network switch is also to transfer, with the arbiter unit, the packet data from the devices in the set of turns. Additionally, the network switch is to determine weight data indicative of the number of turns represented in the set and provide the weight data from the arbiter unit in the first stage to another arbiter unit in a subsequent stage to cause the arbiter unit in the subsequent stage to allocate a number of turns for the transfer of the packet data from the arbiter unit in the first stage.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Scott S. Diesing, Michael A. Parker, Albert S. Cheng, Nan Ni
  • Patent number: 10757039
    Abstract: Apparatuses, methods and storage medium associated with routing data in a switch are provided. In embodiments, the switch may include route lookup circuitry determine a first set of output ports that are available to send a data packet to a destination node. The lookup circuitry may further select, based on respective congestion levels associated with the first set of output ports, a plurality of output ports for a second set of output ports from the first set of output ports. An input queue of the switch may buffer the data packet and route information associated with the second set of output ports. The switch may further include route selection circuitry to select a destination output port from the second set of output ports, based on updated congestion levels associated with the output ports of the second set of output ports. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Albert S. Cheng, Thomas D. Lovett, Michael A. Parker
  • Patent number: 10728178
    Abstract: Apparatuses and methods associated with distributing congestion information in a switch are provided. In embodiments, the switch includes a plurality of ports arranged in a plurality of rows and a plurality of columns. The switch further includes a plurality of daisy-chain buses, individual daisy-chain buses coupling the ports of a respective row to one another in a daisy-chain. The switch further includes a plurality of column buses, individual column buses coupling an individual port of the plurality of ports to the other ports of the respective column. Individual ports of a respective row receive congestion information from the other ports of the row via the respective daisy-chain bus and pass the congestion information to the other ports of the respective column via the respective column bus. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventor: Albert S. Cheng
  • Patent number: 10715452
    Abstract: This disclosure describes systems, devices, methods and computer readable media for enhanced network communication for use in higher performance applications including storage, high performance computing (HPC) and Ethernet-based fabric interconnects. In some embodiments, a network controller may include a transmitter circuit configured to transmit packets on a plurality of virtual lanes (VLs), the VLs associated with a defined VL priority and an allocated share of network bandwidth. The network controller may also include a bandwidth monitor module configured to measure bandwidth consumed by the packets and an arbiter module configured to adjust the VL priority based on a comparison of the measured bandwidth to the allocated share of network bandwidth. The transmitter circuit may be further configured to transmit the packets based on the adjusted VL priority.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: July 14, 2020
    Assignee: INTEL CORPORATION
    Inventors: Albert S. Cheng, Thomas D. Lovett, Michael A. Parker
  • Publication number: 20200050569
    Abstract: In some embodiments, the invention involves using a weighted arbiter switch to provide fairness in passing input streams through a plurality of input ports to an output port. The weighted arbiter switches may be combined in a hierarchical architecture to enable routing through many levels of switches. Each input port has an associated flow counter to count input stream traffic through the input port. An arbiter switch uses the flow counts and weights from arbiter switches at a lower level in the hierarchy to generate a fairly distributed routing of input streams through the output port. Other embodiments are described and claimed.
    Type: Application
    Filed: December 30, 2016
    Publication date: February 13, 2020
    Inventors: Gaspar MORA PORTA, Michael A PARKER, Roberto PENARANDA CEBRIAN, Albert S. CHENG, Francesc GUIM BERNAT
  • Patent number: 10469368
    Abstract: Generally, this disclosure provides systems, methods and computer readable media for switching systems employing distributed routing tables to provide improved support for multiple network topologies, configurations and routing modes. A routing system of a switch, for routing a packet from an input port of a switch to an output port, may include memory modules to store routing tables configured to store entries, each entry configured to store output port identifiers. The routing system may also include a table address generation module configured to select an entry from the routing tables based in part on a first subset of a Destination Location ID (DLID) associated with the packet. The table address generation module may further be configured to select one or more output ports from the selected entries, the selected output ports based in part on a second subset of the DLID.
    Type: Grant
    Filed: March 28, 2015
    Date of Patent: November 5, 2019
    Assignee: INTEL CORPORATION
    Inventor: Albert S. Cheng
  • Patent number: 10454850
    Abstract: Apparatuses, methods and storage medium associated with buffering data in a switch are provided. In embodiments, the switch may include a plurality of queue buffers, a plurality of queues respectively associated with the plurality of queue buffers, a shared buffer, and a queue point controller coupled with the plurality of queue buffers and the shared buffer. In embodiments the queue point controller may be configured to determine an amount of available space in a selected queue buffer of the plurality of queue buffers. The queue point controller may be further configured to allocate at least a portion of the shared buffer to a selected queue that is associated with the selected queue buffer. In embodiments, this allocation may be based on the amount of available space determined in the selected queue buffer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Albert S. Cheng, Thomas D. Lovett, Michael S. Parker, Steven F. Hoover
  • Patent number: 10432582
    Abstract: Technologies for scalable local addressing include one or more managed network devices coupled to one or more computing nodes via high-speed fabric links. A computing node may transmit a data packet including a destination local identifier (DLID) that identifies the destination computing node. The DLID may be 32, 24, 20, or 16 bits wide. The managed network device may determine whether the DLID is within a configurable multicast address space and, if so, forward the data packet to a multicast group. The managed network device may also determine whether the DLID is within a configurable collective address space and, if so, perform a collective acceleration operation. The number of top-most bits set in a multicast mask and the number of additional top-most bits set in a collective mask may be configured. Multicast LIDs may be converted between different bit lengths. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: October 1, 2019
    Assignee: Intel Corporation
    Inventors: Todd M. Rimmer, Albert S. Cheng
  • Publication number: 20190230037
    Abstract: This disclosure describes systems, devices, methods and computer readable media for enhanced network communication for use in higher performance applications including storage, high performance computing (HPC) and Ethernet-based fabric interconnects. In some embodiments, a network controller may include a transmitter circuit configured to transmit packets on a plurality of virtual lanes (VLs), the VLs associated with a defined VL priority and an allocated share of network bandwidth. The network controller may also include a bandwidth monitor module configured to measure bandwidth consumed by the packets and an arbiter module configured to adjust the VL priority based on a comparison of the measured bandwidth to the allocated share of network bandwidth. The transmitter circuit may be further configured to transmit the packets based on the adjusted VL priority.
    Type: Application
    Filed: January 28, 2019
    Publication date: July 25, 2019
    Applicant: Intel Corporation
    Inventors: ALBERT S. CHENG, THOMAS D. LOVETT, MICHAEL A. PARKER
  • Patent number: 10326711
    Abstract: Apparatuses, methods and storage media associated with multiple multi-drop buses in a switch are provided herein. In some embodiments, the switch may include a multi-drop row bus to transmit a plurality of frames in a row dimension of the matrix switch and a multi-drop column bus to transmit the plurality of frames in a column dimension of the matrix switch. The switch may further include an input port to receive the plurality of frames and an output port to output the plurality of frames from the matrix switch. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Albert S. Cheng, Thomas D. Lovett, Michael A. Parker, Steven F. Hoover, Gregory J. Hubbard
  • Patent number: 10237191
    Abstract: This disclosure describes systems, devices, methods and computer readable media for enhanced network communication for use in higher performance applications including storage, high performance computing (HPC) and Ethernet-based fabric interconnects. In some embodiments, a network controller may include a transmitter circuit configured to transmit packets on a plurality of virtual lanes (VLs), the VLs associated with a defined VL priority and an allocated share of network bandwidth. The network controller may also include a bandwidth monitor module configured to measure bandwidth consumed by the packets and an arbiter module configured to adjust the VL priority based on a comparison of the measured bandwidth to the allocated share of network bandwidth. The transmitter circuit may be further configured to transmit the packets based on the adjusted VL priority.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Albert S. Cheng, Thomas D. Lovett, Michael A. Parker
  • Publication number: 20190007317
    Abstract: Technologies for determining a root of congestion include a network switch. The network switch is to operate arbiter units in at least one upstream stage at a packet transfer rate that is greater than a packet transfer rate of an arbiter unit in an output stage, determine whether an input buffer of a remote network switch in communication with the output stage has sustained congestion over a first predefined time period, determine whether an output buffer of the arbiter unit in the output stage has sustained congestion over a second predefined time period, and determine, as a function of whether the input buffer of the remote network switch has sustained congestion and whether the output buffer of the arbiter unit in the output stage has sustained congestion, whether the network switch is a root of congestion.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Inventors: Albert S. Cheng, Michael A. Parker
  • Publication number: 20190007319
    Abstract: Technologies for balancing throughput across input ports include a network switch. The network switch is to generate, for an arbiter unit in a first stage of a hierarchy of stages of arbiter units, turn data indicative of a set of turns in which to transfer packet data from devices connected to input ports of the arbiter unit. The network switch is also to transfer, with the arbiter unit, the packet data from the devices in the set of turns. Additionally, the network switch is to determine weight data indicative of the number of turns represented in the set and provide the weight data from the arbiter unit in the first stage to another arbiter unit in a subsequent stage to cause the arbiter unit in the subsequent stage to allocate a number of turns for the transfer of the packet data from the arbiter unit in the first stage.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 3, 2019
    Inventors: Scott S. Diesing, Michael A. Parker, Albert S. Cheng, Nan Ni
  • Publication number: 20180375801
    Abstract: Apparatuses and methods associated with distributing congestion information in a switch are provided. In embodiments, the switch includes a plurality of ports arranged in a plurality of rows and a plurality of columns. The switch further includes a plurality of daisy-chain buses, individual daisy-chain buses coupling the ports of a respective row to one another in a daisy-chain. The switch further includes a plurality of column buses, individual column buses coupling an individual port of the plurality of ports to the other ports of the respective column. Individual ports of a respective row receive congestion information from the other ports of the row via the respective daisy-chain bus and pass the congestion information to the other ports of the respective column via the respective column bus. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 23, 2015
    Publication date: December 27, 2018
    Inventor: Albert S. CHENG
  • Publication number: 20180287953
    Abstract: Apparatuses, methods and storage medium associated with the placement of data packets in one or more queues of a switch are described herein. In embodiments, the switch may include a plurality of virtual lane (VL) queues (VLQs) and a plurality of generic queues (GQs). A queue manager may be configured to selectively place a packet of a particular VL in a corresponding VLQ or a GQ. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 23, 2014
    Publication date: October 4, 2018
    Inventors: Albert S. CHENG, Michael A. PARKER, Thomas D. LOVETT, Steven F. HOOVER