Abstract: The present invention relates to a method for providing synthesized clock synchronization reference signals in an asynchronous packet based network. Specifically, the present invention pertains to a method of using a timing reference signal as a synchronization reference for a synthesized signal of the same frequency for the purpose of providing synchronous analog communications, such as Voice Over Internet Protocol (VoIP). More specifically, the invention transmits reference signals in Ethernet packets which are then used by recipient devices to synthesize timing signals for synchronization purposes.

Abstract: An uninterruptable power supply for use with an Internet Telephone or Internet Telephone Cable Modem comprises a power supply and a load. The power supply has an AC/DC converter for producing converter DC, and also a rechargeable battery. A DC output multiplexer selects one of such DC sources and furnishes it to the load. The multiplexer has an input control signal for switching the DC source to a battery, and an output indicator indicating when the battery is acting as the DC source. The load includes a controller which generates this test signal at times when it is useful to test the battery, and accepts the indicator signal to know when the battery is providing this current. The controller includes a test function for measuring the reserve charge of the battery by measuring the temporal voltage drop and time of this temporal voltage drop with the use of an A/D converter. Additionally, the controller measures the charge and discharge intervals of the battery.

Abstract: A modular and highly available RAID system has a fiber channel arbitrated loop (FC-AL) interface coupled with a disk array. Fault-tolerant operation is assured. The system provides dual and isolated arbitrated host and storage device loop circuits for redundant, independent input/output (I/O) paths to local and/or remote host computers. Each loop includes bypass circuits which prevent the failure of any device (host computer or storage device) from affecting the operation of loop. Orthogonal data striping may be used to further assure data integrity.

Abstract: A fault tolerant power supply system for providing reliable power to a redundant array of data storage units. The system includes one power supply module for each channel of the array of data storage units. A power supply failure will not impact the ability of the data storage system to recover data due to the ability of the data storage system to reconstruct data in an unavailable channel from the data storage units of each other channel. The use of independent power supplies provides a power supply system which has a power capability equal to the sum of the power requirements of the data storage units, and voltage outputs just sufficient to meet the voltage requirements of the data storage units.

Abstract: A multiprocessing computer system with data storage array systems allowing for linear and orthogonal expansion of data storage capacity and bandwidth by means of a switching network coupled between the data storage array systems and the multiple processors. The switching network provides the ability for any CPU to be directly coupled to any data storage array. By using the switching network to couple multiple CPU's to multiple data storage array systems, the computer system can be configured to optimally match the I/O bandwidth of the data storage array systems to the I/O performance of the CPU's.

Abstract: The present invention is an input/output controller for providing total data integrity for any single point failure. The I/O controller comprises a processor module having two microprocessors, an associated memory, a direct memory access module ("DMA"), and a processor support module ("PSM"); a device drive interface; and a channel interface. The two microprocessors are operated in lockstep as a dual modular redundant processor system. The processors provide true and complement, respectively, addresses, data and control strobes. The PSM compares the true and complement data to detect errors (i.e., corresponding data bits not being a true-complement pair) and generates parity protected data (and checks parity) on the data bus. The PSM also generates and checks dual railed control strobes and provides synchronization of all control strobes and interrupt signals to enable the tru-complement pair of microprocessors to operate in lockstep.

Abstract: An error checking and correcting device for providing group error detection in addition to single error correction and double error detection in a codeword transmitted through a modular communication channel is disclosed. The codeword comprises a plurality of data bits and a plurality of check bits. The modular communication channel comprises a plurality of modules in each of which a group (or cluster) of bits are transferred in parallel. In the preferred embodiment, the code word contains 40 bits with 32 data bits and 8 check bits, and the modular communication channel is a computer memory comprising 10 modules with 4 bits per module. At the transmitter, the check bit generator generates the check bits from the data bits in accordance with an H-matrix which is partitioned into h-submatrices corresponding to group boundaries of the memory. The construction of the h-submatrices is in accordance with rules necessary for group error detection in addition to single error correction and double error detection.