Abstract: An example operation includes one or more of determining, by a transport, a potential impact with an object at a location in a lane on a road and, when a distance away from the location exists within the lane, maneuvering, by the transport, the distance within the lane to avoid the potential impact.

Abstract: An example operation includes one or more of determining, by a first node, a location of an aberration on a second node, determining, by the first node, a third node able to document the aberration for a minimum period of time, notifying, by the first node, the third node to document the aberration for the minimum period of time in a first mode, and receiving, by the first node, the documentation in the first mode.

Abstract: Techniques for efficiently performing full and scaled transforms on data received via full and scaled interfaces, respectively, are described and comprise (1) performing a first transform on a block of first input values to obtain a block of first output values by scaling the block to obtain scaled input values, performing a scaled one-dimensional (1D) transform on each row of the block, and performing a scaled 1D transform on each column of the block; and (2) performing a second transform on a block of second input values to obtain a block of second output values by performing a scaled 1D transform on each row of the block, performing a scaled 1D transform on each column of the block, and scaling the block.

Abstract: Techniques for efficiently performing full and scaled transforms on data received via full and scaled interfaces, respectively, are described. A full transform is a transform that implements the complete mathematical description of the transform. A full transform operates on or provides full transform coefficients. A scaled transform is a transform that operates on or provides scaled transform coefficients, which are scaled versions of the full transform coefficients. The scaled transform may have lower computational complexity whereas the full transform may be simpler to use by applications. The full and scaled transforms may be for a 2D IDCT, which may be implemented in a separable manner with 1D IDCTs. The full and scaled transforms may also be for a 2D DCT, which may be implemented in a separable manner with 1D DCTs. The 1D IDCTs and 1D DCTs may be implemented in a computationally efficient manner.

Abstract: Techniques for efficiently performing full and scaled transforms on data received via full and scaled interfaces, respectively, are described and comprise (1) performing a first transform on a block of first input values to obtain a block of first output values by scaling the block to obtain scaled input values, performing a scaled one-dimensional (1D) transform on each row of the block, and performing a scaled 1D transform on each column of the block; and (2) performing a second transform on a block of second input values to obtain a block of second output values by performing a scaled 1D transform on each row of the block, performing a scaled 1D transform on each column of the block, and scaling the block.

Abstract: A display processor includes an interface unit, an instruction processor, a synchronization unit, at least one processing unit, and a device buffer. The interface unit receives input image data (e.g., from a main memory) and provides output image data for a frame buffer. The instruction processor receives instructions (e.g., in a script or list) and directs the operation of the processing unit(s). The synchronization unit determines the location of a read pointer for the frame buffer and controls the writing of output image data to the frame buffer to avoid causing visual artifacts on an LCD screen. The processing unit(s) may perform various post-processing functions such as region flip, region rotation, color conversion between two video formats (e.g., from YCrCb to RGB), up/down image size rescaling, alpha-blending, transparency, text overlay, and so on.

Abstract: The dual microprocessor system includes one microprocessor configured to perform wireless telephony functions and another configured to perform personal digital assistant (PDA) functions and other non-telephony functions. A memory system and a digital signal processor (DSP) are shared by the microprocessors. By providing a shared memory system, data required by both data microprocessors is conveniently available to both of the microprocessors and their peripheral components thereby eliminating the need to provide separate memory subsystems and further eliminating the need to transfer data back and forth between the separate memory subsystems. By providing a shared DSP, separate DSP devices need not be provided, yet both microprocessors can take advantage of the processing power of the DSP. In a specific example described herein, the microprocessors selectively program the DSP to perform, for example, vocoder functions, voice recognition functions, handwriting recognition functions, and the like.

Abstract: The virtual device architecture provides physical and logical device drivers for interfacing software programs executing on a microprocessor of the mobile telephone of a wireless communication system with any of a wide variety of hardware devices connectable within the mobile telephone. The logical device drivers convert commands received from the software applications to commands appropriate for use by selected hardware devices. The physical device drivers receive the converted commands from the logical device drivers and in response to the received commands directly control the selected hardware devices. In one example described herein, the logical device drivers provide translation of core commands necessary to control the selected hardware devices and extended commands for enhanced control of the hardware devices. The logical device drivers operate to convert the extended commands into core commands prior to forwarding the commands to the physical device drivers.