Abstract: A method of exposing a radiation-sensitive medium through a mask and using an imaging system having a given depth of focus to control for pattern dependent distortion. The steps comprise: providing the radiation-sensitive medium within the depth of focus of the imaging system; providing radiation to the radiation-sensitive medium through the mask; providing the radiation-sensitive medium fully outside the depth of focus of the imaging system; and providing radiation to the radiation-sensitive medium through the mask. Corrections are automatically made by providing the radiation-sensitive medium fully outside the depth of focus of the imaging system, since in that regime the mask operates as a gray-scale mask, with the amount of light passing through any region of the mask dependent on the transmission of the masking pattern in that region.

Abstract: A method of exposing a radiation-sensitive medium through a mask and using an imaging system having a given depth of focus to control for pattern dependent distortion. The steps comprise: providing the radiation-sensitive medium within the depth of focus of the imaging system; providing radiation to the radiation-sensitive medium through the mask; providing the radiation-sensitive medium fully outside the depth of focus of the imaging system; and providing radiation to the radiation-sensitive medium through the mask. Corrections are automatically made by providing the radiation-sensitive medium fully outside the depth of focus of the imaging system, since in that regime the mask operates as a grey-scale mask, with the amount of light passing through any region of the mask dependent on the transmission of the masking pattern in that region.

Abstract: A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion. The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes and continuous horizontally disposed program and recall gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride. The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.