Abstract: An improved circuit for rapidly locking the phase of a reference signal e.sub.r of frequency f.sub.r with the phase of a signal e.sub.VCO in a phase locked loop which comprises a voltage controlled oscillator (VCO) for generating the signal e.sub.VCO of frequency f.sub.VCO, a divide-by-N circuit, for dividing f.sub.VCO by a variable N, a frequency/phase detector responsive to the phases of e.sub.VCO and e.sub.r to supply a control signal e.sub.c to the VCO, a loop filter circuit comprising a resistor and a capacitor for filtering e.sub.c, and logic for changing N to a new value N' in a time interval not less than T. Also provided is a circuit responsive to each change of N for coarse tuning the control signal supplied to the VCO and comprising a voltage generator responsive to each new value N' of N for generating a coarse tuned voltage having a magnitude which, when applied across the capacitor, will change the frequency f.sub.VCO /N to f.sub.VCO /N' to approximate f.sub.r.

Abstract: A frequency synthesizer for controlling the frequency f.sub.0 of a signal e.sub.0 in response to a control signal e.sub.c2 to produce a band of selectable frequencies separated by .DELTA.f between the frequencies f.sub.x and f.sub.y, where (f.sub.x +R.DELTA.f)=f.sub.0 and R is zero or any integer .ltoreq.(f.sub.y -f.sub.x)/.DELTA.f. The invention includes a first generator for generating the signal e.sub.0, a second generator for generating a signal e.sub.1 having a band of selectable frequencies separated by .delta.f, where .delta.f>>.DELTA.f, a frequency subtractor for subtracting f.sub.1 from f.sub.0 to produce a signal e.sub.2 of frequency f.sub.2. Also provided is a third generator for generating a variable preliminary reference signal of frequency f.sub.pr consisting of a band of selectable frequencies separated by M.DELTA.f and lying within the frequency band Mf.sub.x to Mf.sub.y, where (Mf.sub.x +R.multidot.M.DELTA.f)=Mf.sub.r2 ; a divider for dividing Mf.sub.

Abstract: An improvement in a frequency synthesizer comprising a voltage-controlled oscillator (VCO) for generating an output signal S.sub.VCO of frequency F.sub.VCO, a divider for dividing F.sub.VCO in division cycles with each division cycle consisting of the division of F.sub.VCO by N, Y times, and by (N+M), Z times, in an iterative manner to produce a divided output signal S.sub.N of frequency F.sub.N, where the division ratio is ##EQU1## and where N, Y, M and Z are integers, a reference signal generator for generating a reference signal S.sub.R of frequency F.sub.R, and a phase detector responsive to S.sub.N and S.sub.R to produce an output signal whose amplitude is representative of the phase therebetween. The improvement is a control circuit comprising logic for detecting and averaging the output signal from the phase detector during each division of F.sub.VCO in each division cycle to produce a d.c.

Abstract: An improvement in a digital frequency synthesizer comprising a voltage-controlled oscillator (VCO) for producing a signal S.sub.VCO having a frequency f.sub.VCO, a first signal generator for generating a plurality of signals S.sub.AS having a spectrum of frequencies f.sub.AS, all exceeding a given minimum frequency f.sub.M, a mixer responsive to S.sub.VCO and to S.sub.AS to produce an output signal having a frequency (f.sub.VCO .+-.f.sub.AS), a divide-by-N divider responsive to (f.sub.VCO .+-.f.sub.AS) to produce a signal S.sub.N having a frequency f.sub.N, a second signal generator for generating a first reference signal S.sub.R1 having a frequency f.sub.R1, a phase detector responsive to S.sub.N and S.sub.R1 to produce a d.c. control signal E.sub.c whose amplitude varies with the phase relation of S.sub.N and S.sub.R1, and a filter for supplying E.sub.c back to said VCO, the VCO being responsive to E.sub.c to produce an output signal S.sub.VCO of frequency f.sub.VCO where (f.sub.VCO .+-.f.sub.AS )=Nf.sub.

Abstract: An improvement in a phase locked loop comprising a VCO for generating a signal S.sub.VCO of frequency f.sub.VCO, a divider for dividing f.sub.VCO to produce a signal S.sub.N of frequency f.sub.N, a reference signal generator for generating a reference signal S.sub.R of frequency f.sub.R, and with said VCO responsive to a particular value E.sub.c of a variable control signal e.sub.c to cause f.sub.N =f.sub.R for a given value of N, the improvement consisting of a phase/frequency detector for detecting and correcting frequency and phase differences between S.sub.N and S.sub.R to cause f.sub.N =f.sub.R and comprising a three stage left/right shift register responsive to one of signals S.sub.N or S.sub.R to shift binary O's into the first stage thereof in the right direction and responsive to the other of signals S.sub.N or S.sub.R to shift binary 1's into the third stage thereof in the left direction.

Abstract: An improved interrogation means in a range finding system having signal generating means for generating interrogation signals having a first encoded portion and a first basic tone portion. A transponder means responds to said interrogation signal to generate and transmit a responsive signal having a second encoded portion and a second basic tone portion phase synchronous with said first encoded and basic tone portions as received at the transponder. The interrogator means has further means for storing the phases of the first encoded and basic tone portions after transmission thereof and other means for determining the difference between the stored phase of the first encoded portion and the phase of the received second encoded portion.

Abstract: A digitally controlled oscillator for generating a plurality of signals spaced apart by very small frequency increments. The system comprises first means for generating a source signal of frequency f.sub.c, second means responsive to said first signal to produce a first binary output signal of frequency Nf.sub.c /2.sup.n, where n is a variable integer. Also provided are first frequency divider means responsive to said first binary output signal to produce a second binary output signal of frequency Nf.sub.c /2.sup.n+m, where m is another integer and second frequency divider means also responsive to said first signal f.sub.c to produce a third binary output signal of frequency f.sub.c /2.sup.T. Further provided are logic means responsive to said second and third binary output signals to produce a fourth binary output signal of average frequency f.sub.c /2.sup.T +Nf.sub.c /2.sup.n+m.

Abstract: A counter produces, as a function of time, an M bit count of cycles of a periodic signal. A storage device stores a changeable value represented by N bits comprising M higher order bits and N-M lower order bits. An adder produces M bits corresponding to the sum of M counter bits and M higher order bits. A digital-to-analog converter produces an alternating signal corresponding to the value of the M summed bits and N-M lower order bits where the phase of the alternating signal relative to an arbitrary reference signal corresponds to the value stored in the storage device.

Abstract: A phase locked loop includes a voltage-controlled oscillator, and a phase and frequency detector for comprising an input signal pulse wave with a pulse wave from the voltage-controlled oscillator, and for providing a frequency control voltage to the voltage-controlled oscillator. When the pulses overlap, a pulse comparison circuit in the phase and frequency detector produces a frequency "up" signal or a frequency "down" signal proportional to the correction necessary. When the pulses do not overlap, the pulse comparison circuit produces a "non-overlap" signal which effects a rapid frequency correction by causing a current pump in the phase and frequency detector to increase its output to a fixed maximum value, and by causing a loop filter to increase its bandwidth to a fixed maximum value.

Abstract: A phase and frequency detector includes a first flip-flop triggered by a pulse wave from a reference source, and a second flip-flop triggered by a pulse wave from a voltage-controlled oscillator. Gate means couple outputs of the flip-flops back to reset inputs of the flip-flops so that one of the flip-flops generates pulses having widths proportional to the phase difference of the first and second pulse waves. The gate means inhibits the resetting of the triggered flip-flop when the pulses of the first and second pulse waves do not overlap, so that the triggered flip-flop then generates a continuous output useful for rapidly correcting the frequency of the voltage-controlled oscillator.