Abstract: A data processing device contains a time division multiplexed multiport memory. The timing of memory access is defined in time-slots for access to the memory from respective ports. Timing is generated asynchronously with a handshake in response to a ready signal indicating completion of access during a previous time-slot.

Abstract: Method and arrangement for encoding a video signal, wherein a selection (39) is made between the generation of a motion-compensated encoded video signal (I, B, P) and the generation of a higher-resolution picture (IH). The creation of the higher-resolution picture (IH) relies on estimating motion in a series of subsequent pictures (f1,2,3, . . . ) of lower resolution. The higher-resolution picture (IH) is interpolated (38) from these pictures (f1,2,3, . . . ). In a preferred embodiment of the invention, previously determined regions of interest (S(ROI)) are selected (36) from the video signal. The pictures relating to these regions of interest (f1,2,3, . . . ) occupy less memory (33) than entire pictures as picked up by an image sensor (2). A conventional picture memory (33) is sufficient to store the series of pictures (f1,2,3, . . . ) that relates to a certain region of interest. Motion estimation (31) is performed on these pictures and their motion vectors (m) are stored in a vector memory (37).

Abstract: Streaming applications can be represented by process networks (562), in which tasks (450, 451, 456) perform processing of data and communicate these data to each other through FIFO channels (455). During steady-state processing, the process network (562) is fixed (fixed number of tasks (450, 451, 456) and channels (455)). However, the functionality of the application may be changed at run-time implying a different process network topology. In order to avoid the run-time overhead of destroying the entire network (562) and then set up a new one, the network (562) should be dynamically reconfigured. A central task (454) manages the network topology and can issue commands to stop or suspends tasks (450, 451, 456), remove or redirect channels (455), etc. In order to avoid artefacts (e.g. processing display incomplete video frames), the tasks (450, 451, 456) respond to these commands only at certain reconfiguration points (101, 102, 103, 104) in their processing loop.

Abstract: A data processing apparatus executes a program. A number of operations has to be executed at a data dependent points in time. This is implemented by executing a data independent series of instructions at data independent points in time. The series of instructions includes instructions whose completion is dependent on data dependent conditions. Using the conditions it is selected which of the executed instructions cause the operations to be executed. FIG.

Abstract: Noise filtering an image sequence (V1) is provided wherein statistics (S) in at least one image of the image sequence (V1) is determined (11) and at least one filtered pixel value (Pt′) is calculated from a set of original pixel values (Pt, Mi) obtained from the at least one image, wherein the original pixel values (Pt, Mi) are weighted (13) under control (12, &agr;) of the statistics (11).

Abstract: A data processing apparatus is capable of executing an operation that requires many more operands than can be provided in a single instruction. An original instruction starts execution of the operation and other, operand supplying instructions that follow each other in time are used to supply the operands for that operation. When such an operand supplying instruction is not supplied in time, execution of the original instruction is suspended.

Abstract: A signal processing apparatus for processing signals like video, audio or graphics contains signal processor units that produce and consume a stream of data items relating to samples along at least one dimension of an at least one dimensional physical signal. The processor units communicate the data via a memory. Memory address indicators indicating the regions in memory where the data-items are stored are passed between the processor units via a FIFO channel. The control signal outputs of the FIFO channel are use to provide synchronization between the processor units.

Abstract: A data processing device is described which at least comprises a master controller (1), a first functional unit (2) which includes a slave controller (20), a second functional unit (3). The functional units (2,3) share common memory means (11). The device is programmed for executing an instruction by the first functional unit (2), the execution of said instruction involving input/output operations by the first functional unit (3), wherein output data of the first functional unit (2) is processed by the second functional unit (3) during said execution and/or the input data is generated by the second functional (3) unit during said execution.

Abstract: A system encodes an input video signal by subjecting the input video signal to noise reduction to obtain a noise-reduced signal, and encoding a difference between the noise-reduced signal and a prediction signal to produce an encoded signal. The system then decodes the encoded signal to obtain the prediction signal. In the system, the noise-reduction step comprises arithmetically combining the input video signal with the prediction signal.

Abstract: Optimal design method and apparatus for synchronous digital circuits by retiming through selective flipflop positioning and electronic circuit configuration produced by executing the method. The method is for designing a synchronous digital electronic circuit that comprises cells and clocked flipflops interconnected by nets and running at a predetermined clock period, operates as follows. First, uniform-directedly as starting from any cell for any sub-path emanating therefrom its associated delay is accumulated. Next, if for such sub-path the accumulation result exceeds a predetermined integer number of clock periods. The sub-path in question is signalled for subsequent provision with such integer number of flipflops and its accumulation is terminated. Finally, all elementary cell-to-cell connections are provided with flipflops in minimal accordance with said signalling. The invention is particularly advantageous with large circuits such as used in digital video processors and with small clock periods.

Abstract: A variable length decoder device receives a stream of variable-length encoded data segments for successive transient storage. The storage is recurrently accessed under control of successive pointers. A decoder is fed by the storage and decodes a stream of data segments each from a respective encoded data segment. Furthermore, in step with the decoding a next pointer is produced as being directly derived from the accessing through reading of a localizer information. The latter again is produced in a preprocessor that sits before the storage, through localizing the data segments and indicating each segment by an associated localizer.