Abstract: A protection system for a complex process has four redundant protection sets, each of which produces partial reactor trip and partial safeguard actuation signals in pairs of microprocessor-based controllers. Two independent and redundant voting logic trains are provided for the partial reactor trip signals, and two identical, independent and redundant voting logic trains are provided for the partial safeguard actuation signals. Each of the trains includes a pair of redundant microprocessor-based voting logic controllers, each of which receives the partial reactor trip or partial safeguard actuation signals from each of the process protection sets and has a voting processor which generates an intermediate reactor trip or intermediate safeguard actuation signal in response to partial signals from a predetermined number of protection sets. The intermediate signals from the two voting logic controllers in each train are ANDed to generate train signals.

Abstract: A computer network system repetitively distributes messages including uniquely identified blocks of real time data containing a current data image over a broadcast communications network to all real time stations for storage of each repetition of each entire block of data directly in station memory at a unique address space assigned to that uniquely identified block of data. The real time stations receive the blocks of data and alternatively receive other messages from the real time stations. The other messages have a recognized standard protocol, such as the TCP/IP or UDP/IP protocol of the Internet Protocol Suite.

Abstract: An apparatus and method for media access control of a first node in a network on a powerline communication medium. The apparatus includes a priority controller for providing a transmit authorization signal. The authorization signal can be responsive to a unique priority of the first node in relation to other nodes in the network, with the priority controller receiving the node's priority from a node network controller in the first node. The apparatus includes an access controller for receiving the transmit authorization signal and, in response, communicating a transmit request signal to the node network controller. The apparatus also includes an arbitration controller for preventing the node from transmitting to the network until a predetermined number of other nodes have been allowed to precedentially access the network.

Abstract: The operating system clocks in each station on a counter rotating ring network of a distributed processing system are synchronized by latching the count in a free running counter in the network interface of each station at the instant a clock message transmitted by a timekeeper station is received. The timekeeper station then calculates from its operating system time-of-day clock and its free running counter, its time of reception of the clock message, and broadcasts this timekeeper time of reception to the other stations. Each other station calculates its own time of reception from its operating system time of day, and the count in its free running counter, and uses the difference between its time of reception and the timekeeper time of reception to correct its operating system time-of-day clock. Repeater and media propagation delays determined from the dynamic topography of the network are taken into account in calculating the correction factor.

Abstract: Real time periodic messages generated by a plurality of stations on a data communication network and having data periods ranging from a shortest to a longest, where the longest data period is an integer multiple of all the others, are assigned by a server station to transmit time slots, equal in duration to the shortest data period, on a global basis to minimize the number of messages transmitted by all stations during each transmit time slot.

Abstract: Updated images of messages are passed between asynchronous digital processors using dual port shared memory. In the basic form of the invention, three buffers in shared memory are assigned to each message. Where one of the processors is a controller for a data link channel carrying n messages, 2n+1 buffers are provided in free shared memory space with 2 buffers assigned to each message at all times and a common buffer serving as the third buffer for all of the messages. Where linked buffers in local memory of a controller processor receive message updates from a data highway, two buffers in shared memory are assigned to each message and a linked buffer in the controller local memory serves as the third buffer. The buffers containing the message updates are passed between processors by use of a buffer status array in shared memory. A semaphore lock in the array permits only one processor at a time to assign or release buffers.

Abstract: Signals from redundant sensors located throughout a pressurized water reactor (PWR) nuclear power plant are processed in four independent channel sets each of which includes a plurality of independent microcomputers which calibrate, convert to engineering units and calculate partial trip signals and engineered safeguard actuation signals from the sensor signals for use in the conventional voting logic of a plant protection system. The primary and secondary partial trip and engineered safeguard actuation functions associated with various postulated abnormal events are allocated to different independent microcomputers in the channel set for reliability. A test unit common to the channel set automatically, rapidly bypasses and tests each protection function independently while the other protection functions in the channel set remain on-line and also continually tests each microcomputer through a dummy test function performed along with the assigned protection functions.

Abstract: Apparatus and a method for use therein are disclosed for an analog signal processor, particularly one suited for use in nuclear power plant applications, which converts analog process signals to digital form and employs continuous on-line automatic calibration in order to accurately compensate for gain and bias errors occurring in its input analog circuitry.

Abstract: A signal processor which applies non-linear dynamic compensation to an applied analog signal is tested by applying to a reference ramp signal compensation having a transfer function equal to the inverse of the transfer function of the signal processor. This test signal is applied to the signal processor in place of the sensor signal so that after the compensation of the processor is applied to it, the resultant signal should match the reference signal. When the signal processing is carried out digitally in a microcomputer and the response to the test signal is multiplexed back to the tester along with response signals from other microcomputers, variable time skewing of the returned test signal is eliminated by feeding the reference signal through a processing path parallel to that of the test signal and then comparing those two signals in the tester.

Abstract: A serial data communications network in which a plurality of stations communicate among one another in an orderly and collision-free manner on a single serial bus. Each station incorporates an improved bus access circuit to operate in cooperation with the bus access circuit of every other station in the network. The resulting effect as to each station is the assignment of a unique, recurring time window during which the station may initiate a transmission on the serial bus exclusive of all other stations.