Abstract: A semiconductor structure includes an upper-level CMOS transistor layer having a plurality of upper-level N-type and P-type field effect transistors; and a frontside interconnect layer above, and interconnected with, the upper-level transistor layer. The frontside interconnect layer includes frontside power rails and frontside signal wiring, and at least three frontside interconnect layer metal levels. A lower-level CMOS transistor layer has a plurality of lower-level N-type and P-type field effect transistors; and a backside interconnect layer below, and interconnected with, the lower-level transistor layer. The backside interconnect layer includes backside power rails and backside signal wiring and at least three backside interconnect layer metal levels.

Abstract: Electric fields that can cause corrosion of contacts can be compensated for by embodiments of the present invention. For example, voltage waveforms at the contacts can be made to have a zero volt average, and therefore have a zero net electric field. Galvanic voltages generated by dissimilar metals used by a contact and a housing can generate an electric field, and currents motivated by the galvanic electric field can be blocked by capacitively coupling the contacts to their corresponding circuits.

Abstract: A semiconductor structure, system, and method of forming a crescent-shaped dielectric isolation layer for stacked field-effect transistors (FETs). The semiconductor structure may include a transistor including an epi. The semiconductor may also include a substrate, where the epi is directly connected to the substrate. The semiconductor may also include an isolation layer directly connected to the epi and the substrate. The system may include a semiconductor structure. The method may include forming an isolation layer directly connected to a substrate. The method may also include forming a first transistor, where forming the first transistor includes growing a first epi, where the first epi is directly connected to the isolation layer and the substrate.

Abstract: A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

Abstract: The mapping of system memory addresses to physical memory addresses is modeled as a two dimensional mapping array. Each element of the mapping array is assigned a system memory address and a physical memory address to which the system memory address is mapped. The mapping array is arranged to facilitate designation of a portion of the physical memory addresses as spareable physical memory addresses that are employed when there is a memory failure.

Abstract: A semiconductor device includes a top side and a bottom side opposite the top side. A central portion including a semiconductor substrate is disposed between the top side and the bottom side. A component is disposed in the central portion in contact with the semiconductor substrate. The component includes a first electrical connection from the top side and a second electrical connection from the bottom side.

Abstract: Provided herein are compounds, or salts, esters, tautomers, prodrugs, zwitterionic forms, or stereoisomers thereof, as well as pharmaceutical compositions comprising the same. Also provided herein are methods of using the same in modulating (e.g., inhibiting) KRAS (e.g., KRAS having a G12D or G12V mutation or wild-type KRAS) and treating diseases or disorders such as cancers in subjects in need thereof.

Abstract: A system for generating clock signals for a photonic quantum computing system includes a first pump photon source, a first photon-pair source optically coupled to the first pump photon source, and a first photodetector optically coupled to the first photon-pair source. The system also includes a first clock generator electrically coupled to the first photodetector, a second pump photon source, a second photon-pair source optically coupled to the second pump photon source, and a second photodetector optically coupled to the second photon-pair source. The system further includes a second clock generator electrically coupled to the second photodetector and a clock mediator coupled to the first clock generator and the second clock generator.

Abstract: The mapping of system memory addresses to physical memory addresses is modeled as a two dimensional mapping array. Each element of the mapping array is assigned a system memory address and a physical memory address to which the system memory address is mapped. The mapping array is arranged to facilitate designation of a portion of the physical memory addresses as spareable physical memory addresses that are employed when there is a memory failure.

Abstract: A device includes a die stack including a first die including a quantum circuit and a second die including an electronic circuit. The second die and the first die face each other. A coupler is bonded to a first surface of the first die, an optical fiber is coupled to the coupler for coupling light from the optical fiber to the quantum circuit.

Abstract: A semiconductor device includes a stacked transistor structure having field effect transistors on two levels. The two levels include a top side and a bottom side. Active regions are disposed on the bottom side including a leveled surface facing the top side and a faceted backside surface opposite the leveled surface. The leveled surface includes two different semiconductor materials. A backside contact in contact with the faceted backside surface forms a wraparound contact to reduce contact resistance.

Abstract: A semiconductor device includes a stacked transistor structure having field effect transistors on two levels. The two levels include a top side and bottom side. Active regions are disposed on the bottom side. The active regions include a recessed portion therein. A metal cap is disposed within the recessed portion. A contact is disposed within the metal cap to reduce contact resistance.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first transistor having a first source/drain (S/D) region; a second transistor having a second S/D region, the second transistor being stacked on top of the first transistor; and a first S/D contact shared by the first S/D region of the first transistor and the second S/D region of the second transistor, where the first S/D contact has a first portion and a second portion, the first portion being in direct contact with a top surface of the first S/D region of the first transistor and in direct contact with a bottom surface of the second S/D region, and the second portion being in direct contact with an inner sidewall of the second S/D region of the second transistor. A method of manufacturing the semiconductor structure is also provided.

Abstract: A quantum computing system includes a photon processing system, a photon analyzer, and a photon source module coupled to the photon processing system and to the photon analyzer. The photon source module includes at least one photon source configured to discharge one or more photons per trigger signal and a photon multiplexer configured to direct the one or more photons to the photon processing system or to the photon analyzer.

Abstract: Embodiments are directed to wearable electronic devices including a band having a flexible layer and a routing layer coupled to the flexible layer. The routing layer including one or more electrical traces. A first enclosure is coupled to the band at a first opening and includes a first upper enclosure segment coupled to a first side of the band and a first lower enclosure segment coupled to a second side of the band. A processing unit is enclosed within the first enclosure and electrically coupled to the routing layer. A second enclosure is coupled to the band at a second opening and includes a second upper enclosure segment coupled to the first side of the band and a second lower enclosure segment coupled to the second side of the band. A battery is enclosed within the second enclosure and electrically coupled to the processing unit via the routing layer.

Abstract: A photoplethysmographic (PPG) device is disclosed. The PPG device can include one or more light emitters and one or more light sensors to generate the multiple light paths for measuring a PPG signal and perfusion indices of a user. The multiple light paths between each pair of light emitters and light detectors can include different separation distances to generate both an accurate PPG signal and a perfusion index value to accommodate a variety of users and usage conditions. In some examples, the multiple light paths can include the same separation distances for noise cancellation due to artifacts resulting from, for example, tilt and/or pull of the device, a user's hair, a user's skin pigmentation, and/or motion. The PPG device can further include one or more lenses and/or reflectors to increase the signal strength and/or and to obscure the optical components and associated wiring from being visible to a user's eye.

Abstract: A system for generating clock signals for a photonic quantum computing system includes a first pump photon source, a first photon-pair source optically coupled to the first pump photon source, and a first photodetector optically coupled to the first photon-pair source. The system also includes a first clock generator electrically coupled to the first photodetector, a second pump photon source, a second photon-pair source optically coupled to the second pump photon source, and a second photodetector optically coupled to the second photon-pair source. The system further includes a second clock generator electrically coupled to the second photodetector and a clock mediator coupled to the first clock generator and the second clock generator.

Abstract: Use of an AR antagonist, e.g., enzalutamide and other known AR antagonists, for reducing inflammatory genes of COVID-19 subjects is provided by the present invention. In other aspects, the present invention is directed to the use of an AR antagonist, e.g., the drug enzalutamide and other known AR antagonists, to treat lung cancer in a subject. In yet other aspects, the present invention is directed to an AR antagonist, e.g., the drug enzalutamide and other known AR antagonists, as an immunotherapy.

Abstract: A photoplethysmographic (PPG) device is disclosed. The PPG device can include one or more light emitters and one or more light sensors to generate the multiple light paths for measuring a PPG signal and perfusion indices of a user. The multiple light paths between each pair of light emitters and light detectors can include different separation distances to generate both an accurate PPG signal and a perfusion index value to accommodate a variety of users and usage conditions. In some examples, the multiple light paths can include the same separation distances for noise cancellation due to artifacts resulting from, for example, tilt and/or pull of the device, a user's hair, a user's skin pigmentation, and/or motion. The PPG device can further include one or more lenses and/or reflectors to increase the signal strength and/or and to obscure the optical components and associated wiring from being visible to a user's eye.

Abstract: A quantum device includes a cryogenic chamber and a quantum computing module positioned within the cryogenic chamber. The quantum computing module includes a silicon substrate and a quantum circuit (QC) die including a qubit integrated circuit. The QC die is attached to the silicon substrate. An electronic circuit (EC) die including an electronic integrated circuit is attached to the QC die such that the qubit integrated circuit and the electronic integrated circuit face each other. The QC die can be fusion bonded to the EC die. A circuit board (CB) includes a power converter configured to convert input power received from a cryogenic chamber feedthrough to output power that is coupled to the QC die and to the EC die.