Abstract: The clock generator generates an output clock signal of known frequency from an internally generated high frequency signal of unknown frequency and from a low frequency input signal of known frequency. To this end, the clock multiplier first determines the frequency of the internal clock signal from a comparison with the input clock signal. In one arrangement, the frequency of the internal signal is determined by counting a number of clock transitions occurring during the internal signal within one period of the input clock signal. Once the frequency of the internal signal has been determined, the clock multiplier generates an output clock signal based upon the internal clock signal but adjusted in accordance with the newly determined frequency of the internal clock signal. In one arrangement, the clock multiplier employs a programmable divider.