Abstract: A circuit including a first die, an integrated passive device and a second layer. The first die includes a first substrate and active devices. The integrated passive device includes a first layer, a second substrate and passive devices. The second substrate includes vias. The passive devices are implemented at least on the first layer or the second substrate. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The second layer is disposed between the first die and the integrated passive device. The second layer includes pillars. Each of the pillars connects a corresponding one of the active devices to (i) one of the vias, or (ii) one of the passive devices. The first die, the integrated passive device and the second layer are disposed relative to each other to form a stack.

Abstract: Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure provide a package comprising a die attach pad, a die disposed on the die attach pad and a leadframe. The leadframe includes an opening defined therein that exposes a bottom surface of the die attach pad. The leadframe comprises a plurality of bond pads that are exposed at a bottom surface of the leadframe and a plurality of traces that are exposed at the bottom surface of the leadframe. Each trace of the plurality of traces is coupled to a corresponding bond pad of the plurality of bond pads. At least some of the traces are coupled to the die at top surfaces of the at least some of the traces. The leadframe also comprises a plurality of first insulated barriers. Each first insulated barrier is located between (i) a corresponding trace and (ii) a corresponding bond pad coupled to the corresponding trace.

Abstract: Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.

Abstract: A system including a resistive element of a memory cell and a device to access the resistive element of the memory cell. The resistive element includes (i) a first electrode, and (ii) a second electrode. The device includes (i) a first terminal connected to a first contact, and (i) a second terminal connected to a second contact. One or more of the first contact and the second contact of the device is respectively connected to one or more of the first electrode and the second electrode of the resistive element via a third contact. A size of the third contact decreases from the one or more of the first contact and the second contact of the device to the one or more of the first electrode and the second electrode of the resistive element of the memory cell.

Abstract: A resistive random access memory system includes a plurality of bitlines, a plurality of wordlines, and an array of resistive random access memory cells. Each of the resistive random access memory cells in the array includes a transistor and a resistive random access memory element connected in a common gate configuration.

Abstract: Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.

Abstract: Methods and structures for transistors having reduced source contact to gate spacings in semiconductor devices are disclosed. In one embodiment, a method of forming a transistor can include: forming a gate over an active area of the transistor; forming source and drain regions aligned to the gate in the active area; forming source and drain contacts over the source and drain regions, where a spacing from the gate to the source contact of the transistor is less than a spacing from the gate to the drain contact of the transistor; and using one or more modified masks for forming doping profiles for the source region and the drain region.

Abstract: Some of the embodiments of the present disclosure provide an integrated circuit (IC) chip comprising a die, a system on chip (SOC) coupled to the die, and an internal test engine included in the SOC and configured to test the die, wherein one or more components within the IC chip may be configured to be tested by an external test engine coupled to the IC chip. Other embodiments are also described and claimed.

Abstract: A cell of a resistive random access memory including (i) a resistive element and (ii) a switch. The resistive element includes (i) a first electrode, and (ii) a second electrode. The switch includes (i) a first terminal connected to a first contact, and (i) a second terminal connected to a second contact. The second contact is connected to the second electrode of the resistive element via a third contact. The third contact has a shape including a first surface and a second surface that is opposite to the first surface. The shape of the third contact tapers inward from the first surface towards the second surface.

Abstract: Embodiments of the present disclosure provide a package comprising a die attach pad, a die disposed on the die attach pad and a leadframe. The leadframe includes an opening defined therein that exposes a bottom surface of the die attach pad. The leadframe comprises a plurality of bond pads that are exposed at a bottom surface of the leadframe and a plurality of traces that are exposed at the bottom surface of the leadframe. Each trace of the plurality of traces is coupled to a corresponding bond pad of the plurality of bond pads. At least some of the traces are coupled to the die at top surfaces of the at least some of the traces. The leadframe also comprises a plurality of first insulated barriers. Each first insulated barrier is located between (i) a corresponding trace and (ii) a corresponding bond pad coupled to the corresponding trace.

Abstract: Embodiments of the present disclosure provide configurations for a semiconductor package and associated methods of fabricating the semiconductor package. A method of fabricating a semiconductor package includes attaching a semiconductor die to a first substrate, attaching a second substrate to the first substrate, wherein the semiconductor die is embedded in between the first substrate and the second substrate, and forming an electrically insulative structure to substantially encapsulate the semiconductor die, wherein forming the electrically insulative structure is performed subsequent to the second substrate being attached to the first substrate. Additional embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure provide a method comprising forming an electrically conductive structure on a surface of a semiconductor die, attaching the semiconductor die to a substrate, forming a molding compound to encapsulate the semiconductor die, forming an opening in the molding compound, the opening to at least partially expose the electrically conductive structure, and electrically coupling a passive component to the electrically conductive structure through the opening in the molding compound. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.

Abstract: A resistive element of a resistive memory cell. The resistive element includes a contact in communication with a substrate. A bottom electrode is formed on the contact. A transitional metal oxide layer is formed on the bottom electrode. The transitional metal oxide layer includes oxygen vacancies configured to receive donor oxygen atoms. A transition layer formed on the transitional metal oxide layer includes donor oxygen atoms. A reactive metal layer is formed on the transition layer. A top electrode is formed on the transitional metal oxide layer. The transition layer is configured to provide the donor oxygen atoms to the transitional metal oxide layer in response to a voltage being applied to the top electrode.

Abstract: Methods for rounding the bottom corners of a shallow trench isolation structure are described herein. Embodiments of the present invention provide a method comprising forming a first masking layer on a sidewall of an opening in a substrate, removing, to a first depth, a first portion of the substrate at a bottom surface of the opening having the first masking layer therein, forming a second masking layer on the first masking layer in the opening, and removing, to a second depth, a second portion of the substrate at the bottom surface of the opening having the first and second masking layers therein. Other embodiments also are described.

Abstract: A memory including a memory cell and first and second modules. The memory cell has first and second states, where the second state is different than the first state. The first module, subsequent to an initial forming of the memory cell and subsequent to a read cycle or a write cycle of the memory cell, determines a first difference between the first state and a first predetermined threshold or a second difference between the first state and the second state. The second module, subsequent to the first module determining the first difference or the second difference, reforms the memory cell to reset and increase the first difference or the second difference. The second module, during the reforming of the memory cell, applies a first voltage to the memory cell. The first voltage is greater than a voltage applied to the memory cell during the read cycle or the write cycle.

Abstract: A circuit including a first die, an integrated passive device and a second layer. The first die includes a first substrate and active devices. The integrated passive device includes a first layer, a second substrate and passive devices. The second substrate includes vias. The passive devices are implemented at least on the first layer or the second substrate. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The second layer is disposed between the first die and the integrated passive device. The second layer includes pillars. Each of the pillars connects a corresponding one of the active devices to (i) one of the vias, or (ii) one of the passive devices. The first die, the integrated passive device and the second layer are disposed relative to each other to form a stack.

Abstract: An integrated circuit including a die of the integrated circuit, the die including an insulating layer, light emitting diodes, a semiconductor layer, and a control module. The insulating layer includes a first side and a second side. The second side is opposite to the first side. The light emitting diodes are arranged on the first side of the insulating layer. The semiconductor layer is arranged adjacent to the second side of the insulating layer. The light emitting diodes are connected to the semiconductor layer using connections from the first side of the insulating layer to the second side of the insulating layer. The control module is arranged on the semiconductor layer. The control module is configured to output pulse width modulated pulses to the light emitting diodes via the connections.