Abstract: A serial bit stream is first connected to two parallel bit streams using two half rate clocks. The 2-way parallel bit stream is then converted into a five-way parallel bit stream. Therefore, the clock rate of the five-way parallel bit stream is 1/5 of the clock rate of the input bit stream. The input bit stream contains a unique bit sequence or comma to identify the byte and word boundaries. The comma is detected in five way bit stream. Since the clock rate at the five-way bit stream is five times slower than at the input bit stream, substantially slower circuits which operate at lower power can be used to detect the byte boundaries. Therefore, substantially less expensive circuits can be used to adjust the byte boundaries. Quarter rate clocks in combination with two port latches can provide the same bit rate as half-rate clocks, but reduce the lifetime of CMOS circuits substantially less.

Abstract: The present invention is a fully integrated digital filter which interacts with a phase comparator to provide a phase lock loop and data retiming function. The digital filter includes a prescaler, a six bit reversible counter, and a four bit reversible counter. The phase comparator is a D-type edge-triggered flip-flop in which an input data signal clocks the flip-flop and samples a clock signal to determine whether the clock signal leads or lags the input data signal. The clock signal is repeatedly sampled and the digital filter counts the number of leading and lagging signals. The digital filter counts the leading and lagging signals in groups so that the counting rate of the digital filter does not have to be as high as the input data rate. The prescaler groups the bits and the six bit counter determines the number of samples that indicate a clock lead or lag.

Abstract: A clock recovery circuit and demultiplexer circuit which operate at half the data rate of a received data stream. The half-speed clock recovery circuit generates a 0 and 90-degree clock at half the rate of the incoming data. These clocks are sampled by a pair of edge triggered flip-flops using the transitions of the received data as triggers. The outputs of these flip-flops are exclusive OR-ed to provide a signal indicating whether the generated clock leads or lags the received data. The half-speed 1:2 demultiplexer circuit uses the rising and falling edges of a half-speed 90-degree clock to latch the received data through a pair of flip-flops. The outputs of these flip-flops, each triggered by a different edge of the clock, make up two demultiplexed data streams. The clock recovery and demultiplexer circuits of the present invention can be extended to operate at lower clock rates and configured to provide wider demultiplexing.

Abstract: A method of coding control blocks for packet communication wherein the code for control information is restricted to a smaller subset of the coding set used for data blocks. The smaller subset has the property that subfields within the field of the block can be recognized and decoded without the remainder of the encoded block having been received. An 8B/10B code, consisting of 3B/4B and 5B/6B subfields, has the required property. In packet communication, the recognition in an early control subfield that the packet is to be retransmitted allows bit-by-bit retransmission of the encoded packet with only the early subfield being processed.

Abstract: A binary DC balanced code and an encoder circuit for effecting same is described, which translates an 8 bit byte of information into 10 binary digits for transmission over electromagnetic or optical transmission lines subject to timing and low frequency constraints. The significance of this code is that it combines a low circuit count for implementation with excellent performance near the theoretical limits, when measured with the commonly accepted criteria. The 8B/10B coder is partitioned into a 5B/6B plus a 3B/4B coder. The input code points are assigned to the output code points so the number of bit changes required for translation is minimized and can be grouped into a few classes.

Abstract: A multi-stage current mode differential amplifier is disclosed in which each cascaded stage includes a pair of input transistors which have their bases connected to a common voltage source and a pair of control transistors which have their emitters connected to a common current source. A diode-like device is inserted between the collector of a control transistor in one stage and the emitter of an input transistor of the succeeding stage which increases the input impedance seen by the control transistor, thereby permitting an increase in amplification for that stage. In both embodiments, the current signal is amplified at a higher rate than the rate of increase of the bias currents supplied to the emitters of the control transistors in each stage.