Patents by Inventor Albert Yao

Albert Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • LDPMOS structure with enhanced breakdown voltage
    Patent number: 7423319
    Abstract: A semiconductor structure includes a first well region of a first conductivity type overlying a substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first well region, a third well region of the second conductivity type adjacent and spaced apart from the first well region, a first deep well region of the second conductivity type underlying at least portions of the first and the second well regions, a second deep well region of the second conductivity type underlying the third well region and spaced apart from the first deep well region, an insulation region in the first well region, a gate dielectric extending from over the insulation region to over the second well region, and a gate electrode on the gate dielectric.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: September 9, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Robin Hsieh, Tsai Chun Lin, Albert Yao, Pai-Kang Hsu, Tsung-Yi Huang, Ruey-Hsin Liu
  • LDPMOS structure with enhanced breakdown voltage
    Publication number: 20080157197
    Abstract: A semiconductor structure includes a first well region of a first conductivity type overlying a substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first well region, a third well region of the second conductivity type adjacent and spaced apart from the first well region, a first deep well region of the second conductivity type underlying at least portions of the first and the second well regions, a second deep well region of the second conductivity type underlying the third well region and spaced apart from the first deep well region, an insulation region in the first well region, a gate dielectric extending from over the insulation region to over the second well region, and a gate electrode on the gate dielectric.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Inventors: Robin Hsieh, Tsai Chun Lin, Albert Yao, Pai-Kang Hsu, Tsung-Yi Huang, Ruey-Hsin Liu