Patents by Inventor Albert Yeh

Albert Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11729917
    Abstract: A method for optimized filling holes and manufacturing fine lines on a printed circuit board (PCB) carries out the two processes separately. The inner wall of the hole is metalized with reduced graphene oxide (rGO) and then electroplated to fill the hole with copper. The processes are individually performed and thus operating parameters are considered independently. As a result, the copper-plating fillings are evenly compact and the fine lines have square profiles.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: August 15, 2023
    Assignees: TRIALLIAN CORPORATION
    Inventors: Albert Yeh, Nick Yang
  • Publication number: 20220295645
    Abstract: A method for optimized filling holes and manufacturing fine lines on a printed circuit board (PCB) carries out the two processes separately. The inner wall of the hole is metalized with reduced graphene oxide (rGO) and then electroplated to fill the hole with copper. The processes are individually performed and thus operating parameters are considered independently. As a result, the copper-plating fillings are evenly compact and the fine lines have square profiles.
    Type: Application
    Filed: July 15, 2021
    Publication date: September 15, 2022
    Inventors: Albert Yeh, Nick Yang
  • Patent number: 10306768
    Abstract: A method for manufacturing traces of a printed circuit board (PCB) comprises an application of the periodic pulse reverse (PPR) pattern plating process. In the first stage, walls and bottoms in drilled holes of the PCB are modified with reduced graphene oxide (rGO) so that the vias can be formed by filling with copper and a very thin copper layer can be formed on the substrate through the electroplating process. In the second stage, a pattern of very fine traces with width/space less than 30/30 ?m is formed on the thin copper layer and then the traces are formed through the PPR pattern plating process. After removing unwanted copper layer, the traces with even thicknesses and square profiles are achieved and thus conform to requirements of the high density interconnection (HDI) technology.
    Type: Grant
    Filed: January 20, 2018
    Date of Patent: May 28, 2019
    Assignees: TRIALLIAN CORPORATION
    Inventors: Albert Yeh, Nick Yang
  • Publication number: 20180368266
    Abstract: A method for manufacturing traces of a printed circuit board (PCB) comprises an application of the periodic pulse reverse (PPR) pattern plating process. In the first stage, walls and bottoms in drilled holes of the PCB are modified with reduced graphene oxide (rGO) so that the vias can be formed by filling with copper and a very thin copper layer can be formed on the substrate through the electroplating process. In the second stage, a pattern of very fine traces with width/space less than 30/30 ?m is formed on the thin copper layer and then the traces are formed through the PPR pattern plating process. After removing unwanted copper layer, the traces with even thicknesses and square profiles are achieved and thus conform to requirements of the high density interconnection (HDI) technology.
    Type: Application
    Filed: August 28, 2018
    Publication date: December 20, 2018
    Inventors: Albert Yeh, Nick Yang
  • Publication number: 20180310414
    Abstract: A method for manufacturing traces of a printed circuit board (PCB) comprises an application of the periodic pulse reverse (PPR) pattern plating process. In the first stage, walls and bottoms in drilled holes of the PCB are modified with reduced graphene oxide (rGO) so that the vias can be formed by filling with copper and a very thin copper layer can be formed on the substrate through the electroplating process. In the second stage, a pattern of very fine traces with width/space less than 30/30 ?m is formed on the thin copper layer and then the traces are formed through the PPR pattern plating process. After removing unwanted copper layer, the traces with even thicknesses and square profiles are achieved and thus conform to requirements of the high density interconnection (HDI) technology.
    Type: Application
    Filed: January 20, 2018
    Publication date: October 25, 2018
    Inventors: Albert Yeh, Nick Yang
  • Publication number: 20060270079
    Abstract: In one embodiment, a photo-imageable material is deposited on a circuit structure. The photo-imageable material is then exposed to a pattern of radiation, thereby polymerizing portions of the photo-imageable. Un-polymerized portions of the photo-imageable material are then removed to define a solder mask having solder deposition areas. Solder is then deposited in the solder deposition areas. A circuit structure that may be produced in accordance with this method is also disclosed.
    Type: Application
    Filed: May 24, 2005
    Publication date: November 30, 2006
    Inventors: Ling Liu, Albert Yeh, Paul Carson
  • Publication number: 20060096085
    Abstract: In one embodiment, a packaged integrated circuit is tuned by a) incorporating into a packaged integrated circuit design, at least one tunable circuit feature; b) fabricating a packaged integrated circuit in accordance with said packaged integrated circuit design; c) identifying a trimming point on the tunable circuit feature of said packaged integrated circuit, using an x-ray inspection system; d) relating coordinates of the trimming point to coordinates of a visible reference marker; e) utilizing the relationship between the visible reference marker and the trimming point to position a cutting tool over the trimming point; and f) utilizing the cutting tool to make one or more cuts into the packaged integrated circuit, until the tunable circuit feature has been acceptably modified at the trimming point. Other embodiments are also disclosed.
    Type: Application
    Filed: December 16, 2005
    Publication date: May 11, 2006
    Inventors: Albert Yeh, Regina Pabilonia, Robert Kressin, Wei Liu
  • Patent number: 7032713
    Abstract: A battery operated grease gun has a motor that drives a planetary gear assembly that is coupled to a pump assembly that drives a plunger reciprocally in an grease passage to discharge grease through a discharge spout. The pressure in the grease exerts a reaction force on the plunger that will change torque of the motor. The change of the torque of the motor will simultaneously effect voltage applied to the motor. When the voltage in the motor changes, an electronic pressure regulator measures the voltage in the motor to determine the pressure in the grease in the grease passage and stops the motor as the pressure in the grease reaches preset given valves in the pressure regulating device.
    Type: Grant
    Filed: May 22, 2003
    Date of Patent: April 25, 2006
    Assignee: Techway Industrial Co., Ltd.
    Inventors: San-I Huang, Albert Yeh
  • Patent number: 6982831
    Abstract: A spectral interleaver providing flat top spectral transmission passbands and athermal operation is disclosed. The spectral interleaver may comprise a pentagon-shaped birefringent crystal, a polarization beam splitter, and a dielectric mirror at one facet of the crystal. Prisms and polarizing beam splitters can be employed for operation with an unpolarized input beam. The cavity formed by the mirror and the crystal serves as a spectrally dispersive mirror. Front mirror reflectivity is provided by the air-crystal (or other medium-crystal) interface. Proper mirror reflectivities can be achieved by selecting the angle ? of the pentagon-shape crystal. By selecting the proper air space between the mirror and the crystal surface and the crystal length, the interleaver can have a flat top transmission function. A combination of two different crystals which exhibit different thermal-optic effects may be employed such that the total phase retardation is independent of the temperature, leading to athermal operation.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: January 3, 2006
    Assignee: Oplink Communications, Inc.
    Inventors: Pochi Albert Yeh, Zhiling Xu
  • Publication number: 20050114816
    Abstract: In a parallel design process for ICs, plural circuit features to be evaluated are laid out while designing an IC. Plural ICs are then fabricated and packaged. For a first packaged IC, an interior circuit feature coupled to at least one of the plural circuit features to be evaluated is identified. A trimming point on the interior circuit feature is identified using an x-ray inspection system; coordinates of the trimming point are related to coordinates of a visible reference marker; and the relationship between the visible reference marker and the trimming point is used to position a cutting tool over the trimming point. The cutting tool is used to cut into the first packaged IC until the interior circuit feature has been acceptably modified at the trimming point. Operation of the first packaged IC is compared to operation of a second packaged IC. Other parallel design processes are also disclosed.
    Type: Application
    Filed: December 21, 2004
    Publication date: May 26, 2005
    Inventors: Albert Yeh, Regina Pabilonia, Robert Kressin, Wei Liu
  • Patent number: 6859320
    Abstract: Multi-stage, all-pass optical filters used to make low-loss, multi-channel dispersion compensation modules are disclosed. The all-pass optical filters can be ring resonators in waveguides, Gires-Tournois Interferometers (GTIs) in free space form, and the like. The coupling constants and circulating path lengths may also be distinctively varied in each of the series of GTIs, tuning the net dispersion spectrum of the GTI set, such that the sum of the dispersions from the series of GTI's can provide a system with greater bandwidth than the same number of identical GTIs. The local dispersion slope can also be tuned in this manner. Multi-cavity GTIs can also be formed with similar performance enhancing properties.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: February 22, 2005
    Assignee: Oplink Communications, Inc.
    Inventors: Pochi Albert Yeh, Scott Patrick Campbell, Zhiling Xu
  • Patent number: 6840428
    Abstract: A self-adhesive flexible circuit for printed circuit assembly repair is provided. The flexible circuit comprises a carrier film, a circuit trace and an adhesive. The flexible circuit is placeable on a printed circuit board having a circuit assembly and allows simple repair of boards not designed or manufactured correctly and which contain undesirable short or open circuits or misrouted traces. The flexible circuit allows for placement in a desired location, adherence to the circuit board using its own adhesive. The flexible circuit can then be electrically attached, i.e. solder or conductively adhered, to the board.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: January 11, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: Marvin G Wong, Albert A Yeh, Barry Welsh
  • Publication number: 20040231927
    Abstract: A battery operated grease gun has a motor that drives a planetary gear assembly that is coupled to a pump assembly that drives a plunger reciprocally in an grease passage to discharge grease through a discharge spout. The pressure in the grease exerts a reaction force on the plunger that will change torque of the motor. The change of the torque of the motor will simultaneously effect voltage applied to the motor. When the voltage in the motor changes, an electronic pressure regulator measures the voltage in the motor to determine the pressure in the grease in the grease passage and stops the motor as the pressure in the grease reaches preset given valves in the pressure regulating device.
    Type: Application
    Filed: May 22, 2003
    Publication date: November 25, 2004
    Inventors: San-I Huang, Albert Yeh
  • Patent number: 6721079
    Abstract: Fine-tuning of the optical path length in etalon cavities is achieved by slight variations of the cavity's index of refraction. Such index of refraction variations are accomplished by varying the relative gas mixture in gas-gap etalons or UV-exposing doped glass layer(s) in solid etalons or gas-gap+glass etalons.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: April 13, 2004
    Assignee: Accumux Technologies, Inc.
    Inventors: Pochi Albert Yeh, Scott Patrick Campbell
  • Publication number: 20030121953
    Abstract: A self-adhesive flexible circuit for printed circuit assembly repair is provided. The flexible circuit comprises a carrier film, a circuit trace and an adhesive. The flexible circuit is placeable on a printed circuit board having a circuit assembly and allows simple repair of boards not designed or manufactured correctly and which contain undesirable short or open circuits or misrouted traces. The flexible circuit allows for placement in a desired location, adherence to the circuit board using its own adhesive. The flexible circuit can then be electrically attached, i.e. solder or conductively adhered, to the board.
    Type: Application
    Filed: February 19, 2003
    Publication date: July 3, 2003
    Inventors: Marvin G. Wong, Albert A. Yeh, Barry Welsh
  • Publication number: 20030053214
    Abstract: Multi-stage, all-pass optical filters used to make low-loss, multi-channel dispersion compensation modules are disclosed. The all-pass optical filters can be ring resonators in waveguides, Gires-Tournois Interferometers (GTIs) in free space form, and the like. The coupling constants and circulating path lengths may also be distinctively varied in each of the series of GTIs, tuning the net dispersion spectrum of the GTI set, such that the sum of the dispersions from the series of GTI's can provide a system with greater bandwidth than the same number of identical GTIs. The local dispersion slope can also be tuned in this manner. Multi-cavity GTIs can also be formed with similar performance enhancing properties.
    Type: Application
    Filed: August 8, 2002
    Publication date: March 20, 2003
    Applicant: ACCUMUX TECHNOLOGIES, INC.
    Inventors: Pochi Albert Yeh, Scott Patrick Campbell, Zhiling Xu
  • Publication number: 20030042295
    Abstract: A self-adhesive flexible circuit for printed circuit assembly repair is provided. The flexible circuit comprises a carrier film, a circuit trace and an adhesive. The flexible circuit is placeable on a printed circuit board having a circuit assembly and allows simple repair of boards not designed or manufactured correctly and which contain undesirable short or open circuits or misrouted traces. The flexible circuit allows for placement in a desired location, adherence to the circuit board using its own adhesive. The flexible circuit can then be electrically attached, i.e. solder or conductively adhered, to the board.
    Type: Application
    Filed: August 30, 2001
    Publication date: March 6, 2003
    Inventors: Marvin G. Wong, Albert A. Yeh, Barry Welsh
  • Publication number: 20030035212
    Abstract: A spectral interleaver providing flat top spectral transmission passbands and athermal operation is disclosed. The spectral interleaver may comprise a pentagon-shaped birefringent crystal, a polarization beam splitter, and a dielectric mirror at one facet of the crystal. Prisms and polarizing beam splitters can be employed for operation with an unpolarized input beam. The cavity formed by the mirror and the crystal serves as a spectrally dispersive mirror. Front mirror reflectivity is provided by the air-crystal (or other medium-crystal) interface. Proper mirror reflectivities can be achieved by selecting the angle &thgr; of the pentagon-shape crystal. By selecting the proper air space between the mirror and the crystal surface and the crystal length, the interleaver can have a flat top transmission function.
    Type: Application
    Filed: August 7, 2002
    Publication date: February 20, 2003
    Applicant: ACCUMUX TECHNOLOGIES, INC.
    Inventors: Pochi Albert Yeh, Zhiling Xu
  • Publication number: 20030035223
    Abstract: Fine-tuning of the optical path length in etalon cavities is achieved by slight variations of the cavity's index of refraction. Such index of refraction variations are accomplished by varying the relative gas mixture in gas-gap etalons or UV-exposing doped glass layer(s) in solid etalons or gas-gap+glass etalons.
    Type: Application
    Filed: August 8, 2002
    Publication date: February 20, 2003
    Applicant: ACCUMUX TECHNOLOGIES, INC.
    Inventors: Pochi Albert Yeh, Scott Patrick Campbell
  • Patent number: 5641995
    Abstract: A leadless chip carrier is attached to a printed circuit board by soldering its input-output connections to the printed circuit board and also by providing an adhesive between a central portion of the leadless chip carrier and the printed circuit board. This adhesive provides increased mechanical strength to the connection, improving its tolerance to temperature cycling. The adhesive used may be the same solder used to make the input-output connections.
    Type: Grant
    Filed: March 22, 1995
    Date of Patent: June 24, 1997
    Assignee: Hewlett-Packard Company
    Inventors: Katrina Sloma, Martin L. Guth, Albert A. Yeh