Abstract: Systems and methods for monitoring hardware observation points within a System on a Chip (SoC) are disclosed. In one embodiment, a monitoring system includes observers electrically coupled to corresponding hardware observation points. For each observation time period, the observer receives events from a corresponding hardware observation point and outputs observation data indicative of the number of events received. Each observer operates in the same clock and power domain as the corresponding hardware observation point. The hardware monitoring system includes collectors; each collector receives the observation data from a corresponding observer for the observation time period(s). Each collector updates a value of a live-counter based on the observation data and outputs the value of the live-counter. By counting the number of events at the hardware observation points, the monitoring system can enable detailed runtime monitoring, which can be used, e.g.

Abstract: Systems and methods related to hardware controlled power domains in a hardware system (e.g., an integrated circuit) are disclosed. In one embodiment, fully automatic power on and power off of the power domains in the hardware system is provided without software involvement. In this manner, power up and power down times for the power domains are substantially reduced or minimized, which in turn enables shorter active times for the power domains and thus reduced power consumption (e.g., reduced leakage when hardware in the power domains is idle).

Abstract: Systems and methods related to hardware controlled power domains in a hardware system (e.g., an integrated circuit) are disclosed. In one embodiment, fully automatic power on and power off of the power domains in the hardware system is provided without software involvement. In this manner, power up and power down times for the power domains are substantially reduced or minimized, which in turn enables shorter active times for the power domains and thus reduced power consumption (e.g., reduced leakage when hardware in the power domains is idle).

Abstract: Systems and methods for monitoring hardware observation points within a System on a Chip (SoC) are disclosed. In one embodiment, a monitoring system includes observers electrically coupled to corresponding hardware observation points. For each observation time period, the observer receives events from a corresponding hardware observation point and outputs observation data indicative of the number of events received. Each observer operates in the same clock and power domain as the corresponding hardware observation point. The hardware monitoring system includes collectors; each collector receives the observation data from a corresponding observer for the observation time period(s). Each collector updates a value of a live-counter based on the observation data and outputs the value of the live-counter. By counting the number of events at the hardware observation points, the monitoring system can enable detailed runtime monitoring, which can be used, e.g.