Patents by Inventor Alberto Cattani

Alberto Cattani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11094807
    Abstract: A power MOS stage includes a first power MOS device and a second power MOS devices connected in parallel between a first node and a second node, the first power MOS device having a first voltage rating and the second power MOS device having a second voltage rating that is lower than the first voltage rating. A driver circuit is configured to drive control nodes of the first and second power MOS devices in a sequential manner when actuating the power MOS stage by actuating the first power MOS device before actuating the second power MOS device. The control nodes of the first and second power MOS devices are further driven in a sequential manner when deactuating the power MOS stage by deactuating the second power MOS device before deactuating the first power MOS device.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: August 17, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alberto Cattani, Alessandro Gasparini
  • Publication number: 20210226531
    Abstract: A switching converter includes a voltage conversion circuit providing an output voltage from an input voltage and a PWM voltage generated in response to first and second oscillating voltages. The input stage of a transconductor circuit provides an input reference current following a difference between a reference voltage and a voltage dependent on the output voltage and according to a transconductance, and an output stage for providing an output reference current from the input reference current. A phase shifter shifts an oscillating reference voltage according to the output reference current to obtain the first and second oscillating voltages. The transconductance is controlled in response to the input voltage resulting in a change of the input reference current. Compensation for that change is provided by subtracting a variable compensation current from the input reference current, where the variable compensation current is generated in response to the input voltage.
    Type: Application
    Filed: January 12, 2021
    Publication date: July 22, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventors: Alessandro BERTOLINI, Alberto CATTANI, Alessandro GASPARINI
  • Patent number: 11057028
    Abstract: A DC-DC converter includes clock generation circuitry generating first and second clock signals that are out of phase, and a control signal generator generating a switching control signal at an edge of the second clock signal based upon a comparison of an error voltage to a summed voltage. Boost circuitry charges an energy storage component during an on-phase and discharges the energy storage component during an off-phase to thereby generate an output voltage. The on-phase and off-phase are set as a function of the switching control signal. Sum voltage generation circuitry generates a ramp voltage in response to an edge of the first clock signal and generates the summed voltage at an edge of the second clock signal. The sum voltage represents a sum of the ramp voltage and a voltage representative of the current flowing in the energy storage component during the on-phase.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: July 6, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alessandro Bertolini, Alberto Cattani, Stefano Ramorini, Alessandro Gasparini
  • Publication number: 20210184576
    Abstract: First and second n-channel FETs are connected in series between first and second terminals with an intermediate switching node. First and second driver circuits drive gates of the first and second n-channel FETs, respectively, in response to drive signals. The first driver circuit does not implement slew-rate control. A first resistor and capacitor are connected in series between the output of the first driver circuit and an intermediate node. A first electronic switch is connected between the intermediate node and the first terminal. A second electronic switch is connected between the intermediate node and the gate terminal of the first n-channel FET. A second resistor and a third electronic switch are connected in series between the gate terminal of the first n-channel FET and the switching node. A control circuit generates the drive signals and a first, second and third control signal for the first, second and third electronic switch.
    Type: Application
    Filed: December 10, 2020
    Publication date: June 17, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventors: Alberto CATTANI, Alessandro GASPARINI
  • Publication number: 20210099087
    Abstract: A half-bridge converter is controlled by a circuit including a differential circuit receiving a reference signal and a feedback signal which is a function of an output signal from the converter. The half-bridge converter includes high-side and low-side electronic switches. A comparator generates a PWM-modulated signal for controlling the converter as a function of the duty cycle of the PWM-modulated signal in response to a signal at an intermediate node between the high-side and low-side electronic switches and an output of the differential circuit. A gain circuit block coupled between the intermediate node and the input of the comparator applies a ramp signal to the input of the comparator which is a function of the signal at the intermediate node. A variable gain is applied by the gain circuit block in order to keep a constant value for the duty cycle of said PWM-modulated signal irrespective of converter operation.
    Type: Application
    Filed: December 15, 2020
    Publication date: April 1, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventors: Alberto CATTANI, Stefano RAMORINI, Alessandro GASPARINI
  • Publication number: 20210074835
    Abstract: A power MOS stage includes a first power MOS device and a second power MOS devices connected in parallel between a first node and a second node, the first power MOS device having a first voltage rating and the second power MOS device having a second voltage rating that is lower than the first voltage rating. A driver circuit is configured to drive control nodes of the first and second power MOS devices in a sequential manner when actuating the power MOS stage by actuating the first power MOS device before actuating the second power MOS device. The control nodes of the first and second power MOS devices are further driven in a sequential manner when deactuating the power MOS stage by deactuating the second power MOS device before deactuating the first power MOS device.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 11, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventors: Alberto CATTANI, Alessandro GASPARINI
  • Publication number: 20210067148
    Abstract: A DC-DC converter includes clock generation circuitry generating first and second clock signals that are out of phase, and a control signal generator generating a switching control signal at an edge of the second clock signal based upon a comparison of an error voltage to a summed voltage. Boost circuitry charges an energy storage component during an on-phase and discharges the energy storage component during an off-phase to thereby generate an output voltage. The on-phase and off-phase are set as a function of the switching control signal. Sum voltage generation circuitry generates a ramp voltage in response to an edge of the first clock signal and generates the summed voltage at an edge of the second clock signal. The sum voltage represents a sum of the ramp voltage and a voltage representative of the current flowing in the energy storage component during the on-phase.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 4, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventors: Alessandro BERTOLINI, Alberto CATTANI, Stefano RAMORINI, Alessandro GASPARINI
  • Publication number: 20210036601
    Abstract: A circuit is operated by receiving an input reference signal at an input node, determining a scaling ratio based on the input reference signal, generating a digital input signal as a function of the determined scaling ratio, converting the digital input signal into an analog signal that is a scaled replica of the input reference signal, and providing the analog signal at an output node of the circuit and then, after a duration of time, coupling the input reference signal to the output node.
    Type: Application
    Filed: October 16, 2020
    Publication date: February 4, 2021
    Inventors: Giuseppe Calcagno, Alberto Cattani, Giuseppina Sapone
  • Patent number: 10897200
    Abstract: A half-bridge converter is controlled by a circuit including a differential circuit receiving a reference signal and a feedback signal which is a function of an output signal from the converter. The half-bridge converter includes high-side and low-side electronic switches. A comparator generates a PWM-modulated signal for controlling the converter as a function of the duty cycle of the PWM-modulated signal in response to a signal at an intermediate node between the high-side and low-side electronic switches and an output of the differential circuit. A gain circuit block coupled between the intermediate node and the input of the comparator applies a ramp signal to the input of the comparator which is a function of the signal at the intermediate node. A variable gain is applied by the gain circuit block in order to keep a constant value for the duty cycle of said PWM-modulated signal irrespective of converter operation.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: January 19, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alberto Cattani, Stefano Ramorini, Alessandro Gasparini
  • Publication number: 20210013808
    Abstract: First and second FETs of a half-bridge are series connected between first and second terminals and are gate driven, respectively, by first and second drivers. An inductance is connected to the intermediate node of the half-bridge. Power supply for the second driver circuit is a supply voltage generated by a voltage regulator as a function of the voltage between the first and the second terminal. Power supply for the first driver circuit is a supply voltage generated by a bootstrap capacitor having a first terminal connected via a first switch to receive the supply voltage output from the voltage regulator and a second terminal connected to the intermediate node. The first terminal of the bootstrap capacitor is further connected by a second switch to receive a second supply voltage. A control circuit generates control signals for the first and second driver circuits and the first and second switches.
    Type: Application
    Filed: July 9, 2020
    Publication date: January 14, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventors: Alberto CATTANI, Alessandro GASPARINI
  • Publication number: 20210006163
    Abstract: A first switch couples an input node receiving a main control signal for a main switching stage of a multi-phase converter to an output node delivering a secondary control signal for a secondary switching stage following actuation of the secondary switching stage. A second switch couples the output node to a capacitor during a time period of actuation/deactuation of the secondary switching stage. Current is sourced to the capacitor during the actuation time period or sunk from the capacitor during the deactuation time period. The sourced or sunk current may be generated proportional to the main control signal.
    Type: Application
    Filed: June 30, 2020
    Publication date: January 7, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventor: Alberto CATTANI
  • Patent number: 10826384
    Abstract: A circuit includes an input node configured to receive an input reference signal. An output node is configured to provide a replica of the input reference signal with a respective scaling ratio to the input reference signal at the input node. A digital-to-analog converter has a reference input configured to receive the input reference signal from the input node, a digital input configured to receive a digital input signal having a digital signal value, and a digital-to-analog converter output configured to provide an output signal from the digital-to-analog converter resulting from conversion to analog of the digital input signal. The output node of the circuit is configured to sense the output signal from the digital-to-analog converter and to provide the replica of the input reference signal at the output node.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: November 3, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giuseppe Calcagno, Alberto Cattani, Giuseppina Sapone
  • Patent number: 10680521
    Abstract: An inductor and a shunt switch circuit are connected in parallel between an input node and an intermediate node. A first power transistor is connected between the intermediate node and a ground node. A second power transistor is connected between the intermediate node and an output node. The first and second power transistors are driven in response to a pulse width modulation (PWM) drive cycle having an on-time and an off-time. The input node receives a DC input voltage and a DC output voltage is generated at the output node. A control circuit senses the input and output nodes and determines whether the DC input voltage is within a threshold voltage of the DC output voltage. In response to that determination, the shunt switch circuit is turned on only during the off-time of the PWM drive cycle.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: June 9, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alessandro Bertolini, Alberto Cattani
  • Patent number: 10566940
    Abstract: A switching amplifier, such as a Class D amplifier, includes a current sensing circuit. The current sensing circuit is formed by replica loop circuits that are selectively coupled to corresponding output inverter stages of the switching amplifier. The replica loop circuits operated to produce respective replica currents of the output currents generated by the output inverter stages. A sensing circuitry is coupled to receive the replica currents from the replica loop circuits and operates to produce an output sensing signal as a function of the respective replica currents.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: February 18, 2020
    Assignee: StMicroelectronics S.r.l.
    Inventors: Stefano Ramorini, Alberto Cattani, Germano Nicollini, Alessandro Gasparini
  • Publication number: 20200028432
    Abstract: A circuit includes an input node configured to receive an input reference signal. An output node is configured to provide a replica of the input reference signal with a respective scaling ratio to the input reference signal at the input node. A digital-to-analog converter has a reference input configured to receive the input reference signal from the input node, a digital input configured to receive a digital input signal having a digital signal value, and a digital-to-analog converter output configured to provide an output signal from the digital-to-analog converter resulting from conversion to analog of the digital input signal. The output node of the circuit is configured to sense the output signal from the digital-to-analog converter and to provide the replica of the input reference signal at the output node.
    Type: Application
    Filed: July 8, 2019
    Publication date: January 23, 2020
    Inventors: Giuseppe Calcagno, Alberto Cattani, Giuseppina Sapone
  • Publication number: 20190372535
    Abstract: A switching amplifier, such as a Class D amplifier, includes a current sensing circuit. The current sensing circuit is formed by replica loop circuits that are selectively coupled to corresponding output inverter stages of the switching amplifier. The replica loop circuits operated to produce respective replica currents of the output currents generated by the output inverter stages. A sensing circuitry is coupled to receive the replica currents from the replica loop circuits and operates to produce an output sensing signal as a function of the respective replica currents.
    Type: Application
    Filed: August 13, 2019
    Publication date: December 5, 2019
    Applicant: STMicroelectronics S.r.l.
    Inventors: Stefano RAMORINI, Alberto CATTANI, Germano NICOLLINI, Alessandro GASPARINI
  • Patent number: 10498316
    Abstract: An auto-tuned ramp generator and a method for generating a sawtooth signal are provided. In the method and apparatus, a sawtooth signal is compared to a first reference voltage and a second reference voltage. In response to determining that the sawtooth signal does not exceed the first reference voltage, the voltage level of the sawtooth signal is increased. In response to determining that the sawtooth signal exceeds the second reference voltage, the voltage level of the sawtooth signal is decreased. The voltage level the sawtooth signal is retained if the sawtooth signal remains between the first and second reference voltages.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: December 3, 2019
    Assignee: STMicroelectronics S.R.L.
    Inventors: Alberto Cattani, Alessandro Gasparini, Alessandro Bertolini
  • Publication number: 20190348915
    Abstract: A half-bridge converter is controlled by a circuit including a differential circuit receiving a reference signal and a feedback signal which is a function of an output signal from the converter. The half-bridge converter includes high-side and low-side electronic switches. A comparator generates a PWM-modulated signal for controlling the converter as a function of the duty cycle of the PWM-modulated signal in response to a signal at an intermediate node between the high-side and low-side electronic switches and an output of the differential circuit. A gain circuit block coupled between the intermediate node and the input of the comparator applies a ramp signal to the input of the comparator which is a function of the signal at the intermediate node. A variable gain is applied by the gain circuit block in order to keep a constant value for the duty cycle of said PWM-modulated signal irrespective of converter operation.
    Type: Application
    Filed: May 8, 2019
    Publication date: November 14, 2019
    Applicant: STMicroelectronics S.r.l.
    Inventors: Alberto CATTANI, Stefano RAMORINI, Alessandro GASPARINI
  • Patent number: 10439569
    Abstract: A switching amplifier, such as a Class D amplifier, includes a current sensing circuit. The current sensing circuit is formed by replica loop circuits that are selectively coupled to corresponding output inverter stages of the switching amplifier. The replica loop circuits operated to produce respective replica currents of the output currents generated by the output inverter stages. A sensing circuitry is coupled to receive the replica currents from the replica loop circuits and operates to produce an output sensing signal as a function of the respective replica currents.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: October 8, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Stefano Ramorini, Alberto Cattani, Germano Nicollini, Alessandro Gasparini
  • Publication number: 20190222204
    Abstract: An auto-tuned ramp generator and a method for generating a sawtooth signal are provided. In the method and apparatus, a sawtooth signal is compared to a first reference voltage and a second reference voltage. In response to determining that the sawtooth signal does not exceed the first reference voltage, the voltage level of the sawtooth signal is increased. In response to determining that the sawtooth signal exceeds the second reference voltage, the voltage level of the sawtooth signal is decreased. The voltage level the sawtooth signal is retained if the sawtooth signal remains between the first and second reference voltages.
    Type: Application
    Filed: January 17, 2018
    Publication date: July 18, 2019
    Inventors: Alberto CATTANI, Alessandro GASPARINI, Alessandro BERTOLINI