Abstract: Closed loop dynamic power management is accomplished via a pass/fail detector executing test code in a chip to verify operation of the chip, and a voltage regulator working in a regulation loop with the pass/fail detector to regulate power by setting Vdd to a minimum allowable value for the chip. If the chip passes the test, power is regulated by decreasing Vdd and executing the test code until the chip fails to execute the test code. When the chip fails the test, Vdd is increased prior to being set as the minimum Vdd.