Abstract: The present invention concerns the antidiabetic activity of compounds type A, namely of 8-?-D-glucosylgenistein, which is not toxic to eukaryotic cells and has demonstrated to produce complete normalization of fasting hyperglycaemia, to reduce excessive postprandial glucose excursion, to increase glucose-induced insulin secretion and insulin sensitivity. An alternative synthesis for this molecular entity and its binding ability to ?-amyloid oligomers is also included in the present invention, which also comprises Genista tenera ethyl acetate extract for use as antihyperglycaemic agent i.e. for lowering blood glucose levels in mammals that are pre-diabetic or have type 2 or type 1 diabetes. The inhibitory activity of ?-glucosidase by Genista tenera ethyl acetate and butanol extracts and that of glucose-6-phosphastase by these two extracts and the diethyl ether plant extract is also part of the present invention.

Abstract: The present invention concerns the antidiabetic-activity of compounds type A, namely of 8-?-D-glucosylgenistein, which is not toxic to eukaryotic cells and has demonstrated to produce complete normalization of fasting hyperglycaemia, to reduce excessive postprandial glucose excursion, to increase glucose-induced insulin secretion and insulin sensitivity. An alternative synthesis for this molecular entity and its binding ability to ?-amyloid oligomers is also included in the present invention, which also comprises Genista tenera ethyl acetate extract for use as antihyperglycaemic, agent i.e. for lowering blood glucose levels in mammals that are pre-diabetic or have type 2 or type 1 diabetes. The inhibitory activity of ?-glucosidase by Genista tenera ethyl acetate and butanol extracts and that of glucose-6-phosphatase by these two extracts and the diethyl ether plant extract is also part of the present invention.

Abstract: One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

Abstract: In one implementation, a power converter includes an output stage integrated circuit (IC) on a group III-V die, and a driver IC for driving the output stage IC, the driver IC fabricated on a group IV die. The power converter also includes a composite power switch split between the group III-V die and the group IV die, wherein a depletion mode group III-V transistor of the composite power switch is monolithically integrated in the group III-V die, and a group IV control switch of the composite power switch is monolithically integrated in the group IV die. As a result, the depletion mode group III-V transistor may be operated as an enhancement mode transistor.

Abstract: In one implementation, a power converter includes an output stage integrated circuit (IC) in a group III-V die including a depletion mode group III-V transistor, and a driver IC in a group IV die. The driver IC is configured to drive the output stage IC. In addition, a group IV control switch in the group IV die is cascoded with the depletion mode group III-V transistor. The power converter further includes an overcurrent protection circuit for the depletion mode group III-V transistor, the overcurrent protection circuit monolithically integrated in the group IV die.

Abstract: One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (PET), such as a silicon PET, stacked atop a III-nitride transistor, such that a drain of the PET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

Abstract: One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

Abstract: One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

Abstract: The present invention concerns the antidiabetic-activity of compounds type A, namely of 8-?-D-glucosylgenistein, which is not toxic to eukaryotic cells and has demonstrated to produce complete normalization of fasting hyperglycaemia, to reduce excessive postprandial glucose excursion, to increase glucose-induced insulin secretion and insulin sensitivity. An alternative synthesis for this molecular entity and its binding ability to ?-amyloid oligomers is also included in the present invention, which also comprises Genista tenera ethyl acetate extract for use as antihyperglycaemic, agent i.e. for lowering blood glucose levels in mammals that are pre-diabetic or have type 2 or type 1 diabetes. The inhibitory activity of ?-glucosidase by Genista tenera ethyl acetate and butanol extracts and that of glucose-6-phosphatase by these two extracts and the diethyl ether plant extract is also part of the present invention.

Abstract: One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (PET), such as a silicon PET, stacked atop a III-nitride transistor, such that a drain of the PET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

Abstract: One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (FET), such as a silicon FET, stacked atop a III-nitride transistor, such that a drain of the FET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

Abstract: In one implementation, a power converter includes an output stage integrated circuit (IC) in a group III-V die including a depletion mode group III-V transistor, and a driver IC in a group IV die. The driver IC is configured to drive the output stage IC. In addition, a group IV control switch in the group IV die is cascoded with the depletion mode group III-V transistor. The power converter further includes an overcurrent protection circuit for the depletion mode group III-V transistor, the overcurrent protection circuit monolithically integrated in the group IV die.

Abstract: In one implementation, a power converter includes an output stage integrated circuit (IC) on a group III-V die, and a driver IC for driving the output stage IC, the driver IC fabricated on a group IV die. The power converter also includes a composite power switch split between the group III-V die and the group IV die, wherein a depletion mode group III-V transistor of the composite power switch is monolithically integrated in the group III-V die, and a group IV control switch of the composite power switch is monolithically integrated in the group IV die. As a result, the depletion mode group III-V transistor may be operated as an enhancement mode transistor.

Abstract: One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (FET), such as a silicon FET, stacked atop a III-nitride transistor, such that a drain of the FET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

Abstract: One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

Abstract: Pesticidal compounds of general formula (I) Wherein ?represents a double bond; A— represents ?C(R5)—C(?O)—, wherein R represents hydrogen or halogen, R1 and R2 represent, independently, hydrogen, halogen, alkoxy, substituted alkoxy or an ester group; or R1 and R2, together with the carbon atoms to which they are attached, represent an oxirane ring; or R1 and R2, taken together, represent an alkylidenedioxy or substituted alkylidenedioxy group; and R3 represents —CH2R6, wherein R6 represents an ester group, oxiranyl, or a group of formula wherein R7 represents hydrogen or alkyl, R8 represents phenylsulfanyl, phenylselenyl, phenylsulfoxy or phenylselenoxy, and R9 represents hydrogen, ethoxycarbonyl or carbamoyl and R4 represents, independently, hydrogen, alkoxy or substituted alkoxy; and methods of making the compounds of formula (I) and methods for controlling pests wherein the pest dies as a result of contact with a compound of formula (I).

Abstract: A power module that includes a power circuit assembly in which power components are electrically and mechanically connected without wires.

Abstract: A method for controlling pests, the method comprising applying an effective amount to pests or their locus of one or more compounds of general formula (I) wherein R1 and R2 represent, independently from each other, hydrogen, halogen, alkoxy, substituted alkoxy or an ester group; R1 and R2, together with the carbon atoms to which they are attached, represent an oxirane ring; R1 and R2, taken together, represent an akylidenedioxy or substituted alkylidenedioxy group; and R3 represents —CH2R6, wherein R6 represents an ester group, oxiranyl, or a group of formula wherein R7 represents hydrogen or alkyl, R8 represents phenylsulfanyl, phenylselenyl, phenylsulfoxy or phenylselenoxy, and R9 represents hydrogen, ethoxycarbonyl or carbamoyl; and R4 represents, independently, hydrogen, alkoxy or substituted alkoxy, or R1 and R4, taken together, represent an alkylidenedioxy or a substituted alkylidenedioxy group; wherein the pest dies as a result of contact with the compound.

Abstract: A sensor apparatus and method that can measure either a linear position or an angular position of a device. A linear array of galvanomagnetic sensing elements is fixedly mountable adjacent the device. A target is connectable to the device such that the target moves adjacent a surface of the linear array in response to movement of the device and is shaped so that a magnetic flux density curve resulting from excitation of the sensing elements includes a peak and/or a valley. A first circuit excites each of the sensing elements, and a second circuit measures a magnetic flux density value at each of the sensing elements. A maximum and/or a minimum of the flux density curve indicates the position of the device.

Abstract: Galvanomagnetic sensor array system and method for providing data interface to a basic sensor array are provided. The sensor system includes an array of galvanomagnetic elements, and a processor coupled to receive each output signal from the array of galvanomagnetic elements. The processor and array of galvanomagnetic elements are integrated in a single semiconductor die.