Abstract: A clock network synthesis method and apparatus corrects for clock skew and impedance differences. A method includes identifying clock networks having more active elements as compared to other clock networks of a plurality of clock networks, for those identified clock networks, identifying a pattern of active elements therein as transversed by a clock signal, and for those unidentified clock networks in the correlated clock networks, adding active elements such that those added active elements transversed by the clock signal match those transversed in the identified clock networks. A method for preventing clock skew and impedance differences includes performing a clock balancing, identifying each related node across a sub-network, identifying each input driven via the identified related nodes, and adding one or more active elements to one or more nodes until each element in the identified related nodes drives a same number of inputs.

Abstract: A clock network synthesis method and apparatus corrects for clock skew and impedance differences. A method includes identifying clock networks having more active elements as compared to other clock networks of a plurality of clock networks, for those identified clock networks, identifying a pattern of active elements therein as transversed by a clock signal, and for those unidentified clock networks in the correlated clock networks, adding active elements such that those added active elements transversed by the clock signal match those transversed in the identified clock networks. A method for preventing clock skew and impedance differences includes performing a clock balancing, identifying each related node across a sub-network, identifying each input driven via the identified related nodes, and adding one or more active elements to one or more nodes until each element in the identified related nodes drives a same number of inputs.

Abstract: A method (100) and apparatus (600) estimates power of an architectural design. Power functions are generated (step 102) for standard components (20) by synthesizing to a power-measurable implementation (step 202). A behavioral description is simulated (step 106) to produce switching activity and then parsed (step 108) to compute power from power functions of instantiated standard components (steps 109, 114, 118) from switching activity (step 116). Behavioral operations are parsed (step 108) into short and long blocks based on the number of operations. Short blocks are precompiled (step 110) to produce an RTL implementation including standard components. Power is estimated from switching activity at ports and inferred nodes (step 420). Long blocks are synthesized to produce power-measurable implementations (step 112). Power is estimated with a power function from weighted switching activity at each input (steps 508, 512-514).

Abstract: A method of selecting device (14-16, 18-24, 28-30) threshold voltages for high speed and low overall power involves identifying (42) the critical paths by predetermined timing criteria. All transistors have an initial, typically high, threshold voltage (40). Transistors outside the critical paths keep the initial high threshold voltages to minimize static power drain. The transistors in the critical path are selected (43) according to a predetermined sorting function to have a low threshold voltage and thereby switch faster. Although the lower threshold voltage devices consume more static power in standby mode, the power drain is accepted as a trade-off in favor of increased speed through the critical path. The supply voltage is reduced to minimize dynamic power. The integrated circuit is thus optimized to run at a higher frequency with lower overall power consumption.

Abstract: A method of generating power vectors to calculate power dissipation for a circuit cell is provided. The method involves formulating the Boolean equations (30) that describe the logical operation for a circuit cell (10). Primitive power vectors that cause an output to transition are generated (32) using Boolean difference functions. Internal power vectors that cause an internal node to transition without transitioning the output are generated (34) using Boolean difference functions. Static power vectors with all possible steady state inputs are also generated (36). The power vectors are minimized (38) to eliminate redundant vectors. The resulting power vectors can be used in a circuit simulation in evaluating (40) the power dissipation of a designed logic circuit.

Abstract: A low power flip-flop circuit is disclosed including a clocked flip-flop (10) and switching circuit (40, 60) with control inputs coupled to the data input and data output of the flip-flop to determine whether or not the data input to the flip-flop is changing. Any clock pulse during periods when the data input is not changing consumes power without providing a useful function. The switching circuit passes clock pulses to a clock input of the flip-flop only when new data is present to be latched into the flip-flop, i.e. data input state and data output state disagree. The switching circuit blocks clock pulses to the flip-flop when the data to the flip-flop is not changing and thereby saves power consumption.