Patents by Inventor Alberto Jose' Di Martino
Alberto Jose' Di Martino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11495310Abstract: A method for erasing non-volatile memory including applying a first voltage pulse to a non-volatile memory cell to perform a first erase operation of the non-volatile memory cell and determining that a threshold voltage of the non-volatile memory cell is greater than a test voltage. The method further comprising updating a dedicated memory location with a value; and checking the non-volatile memory cell to determine whether the threshold voltage of the non-volatile memory cell is less than an erase-verify voltage to verify that the first erase operation has been performed successfully.Type: GrantFiled: October 22, 2021Date of Patent: November 8, 2022Assignee: STMICROELECTRONICS S.R.L.Inventors: Giovanni Matranga, Gianbattista Lo Giudice, Rosario Roberto Grasso, Alberto Jose' Di Martino
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Patent number: 11328778Abstract: A method of operating a non-volatile memory including having a first set of non-volatile memory cells and a second set of non-volatile memory cells. The first set of non-volatile memory cells and second set of non-volatile memory cells are associated with host addresses. Voltage levels are determined to erase the first and second sets of non-volatile memory cells. The first and second sets of non-volatile memory cells are disassociated from the host addresses. And, the first set of non-volatile memory cells is associated to another address based on the voltage level effective to erase the non-volatile memory cells.Type: GrantFiled: July 9, 2020Date of Patent: May 10, 2022Assignee: STMICROELECTRONICS S.R.L.Inventors: Gianbattista Lo Giudice, Giovanni Matranga, Rosario Roberto Grasso, Alberto Jose' Di Martino
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Publication number: 20220044743Abstract: A method for erasing non-volatile memory including applying a first voltage pulse to a non-volatile memory cell to perform a first erase operation of the non-volatile memory cell and determining that a threshold voltage of the non-volatile memory cell is greater than a test voltage. The method further comprising updating a dedicated memory location with a value; and checking the non-volatile memory cell to determine whether the threshold voltage of the non-volatile memory cell is less than an erase-verify voltage to verify that the first erase operation has been performed successfully.Type: ApplicationFiled: October 22, 2021Publication date: February 10, 2022Inventors: Giovanni Matranga, Gianbattista Lo Giudice, Rosario Roberto Grasso, Alberto Jose' Di Martino
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Publication number: 20220011943Abstract: A method of operating a non-volatile memory including having a first set of non-volatile memory cells and a second set of non-volatile memory cells. The first set of non-volatile memory cells and second set of non-volatile memory cells are associated with host addresses. Voltage levels are determined to erase the first and second sets of non-volatile memory cells. The first and second sets of non-volatile memory cells are disassociated from the host addresses. And, the first set of non-volatile memory cells is associated to another address based on the voltage level effective to erase the non-volatile memory cells.Type: ApplicationFiled: July 9, 2020Publication date: January 13, 2022Inventors: Gianbattista Lo Giudice, Giovanni Matranga, Rosario Roberto Grasso, Alberto Jose' Di Martino
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Patent number: 11183255Abstract: A method for erasing non-volatile memory including applying a first voltage pulse to a non-volatile memory cell to perform a first erase operation of the non-volatile memory cell and determining that a threshold voltage of the non-volatile memory cell is greater than a test voltage. The method further comprising updating a dedicated memory location with a value; and checking the non-volatile memory cell to determine whether the threshold voltage of the non-volatile memory cell is less than an erase-verify voltage to verify that the first erase operation has been performed successfully.Type: GrantFiled: July 9, 2020Date of Patent: November 23, 2021Assignee: STMICROELECTRONICS S.R.L.Inventors: Giovanni Matranga, Gianbattista Lo Giudice, Rosario Roberto Grasso, Alberto Jose′ Di Martino
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Patent number: 9697896Abstract: A phase change non-volatile memory device has a memory array with a plurality of memory cells arranged in rows and columns, a column decoder and a row decoder designed to select columns, and, respectively, rows of the memory array during operations of programming of corresponding memory cells. A control logic, coupled to the column decoder and the row decoder, is designed to execute a sequential programming command, to control the column decoder and row decoder to select one column of the memory array and execute sequential programming operations on a desired block of memory cells belonging to contiguous selected rows of the selected column.Type: GrantFiled: February 16, 2015Date of Patent: July 4, 2017Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS PTE LTD.Inventors: Antonino Conte, Alberto Jose′ Di Martino, Kailash Khairnar
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Patent number: 9484872Abstract: An amplifier circuit may include an input amplification stage comprising a first amplifier having first and second differential inputs and a first output, and a second amplifier having first and second differential inputs and a second output. The amplifier circuit also includes an output amplification stage having first and second inputs respectively coupled to the first and second outputs of the input amplification stage, and an output configured to supply an output voltage based upon the input voltage by an amplification factor. The amplifier circuit comprises a feedback stage with a common-mode control stage configured to implement a comparison between the first differential voltage and the second differential voltage, and a reference voltage, and generate respective regulation currents on the first and second inputs of the output amplification stage to compensate for a common-mode variation of the first differential voltage and the second differential voltage.Type: GrantFiled: December 15, 2015Date of Patent: November 1, 2016Assignee: STMICROELECTRONICS S.R.L.Inventors: Antonino Conte, Alberto Jose' Di Martino
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Publication number: 20150243356Abstract: A phase change non-volatile memory device has a memory array with a plurality of memory cells arranged in rows and columns, a column decoder and a row decoder designed to select columns, and, respectively, rows of the memory array during operations of programming of corresponding memory cells. A control logic, coupled to the column decoder and the row decoder, is designed to execute a sequential programming command, to control the column decoder and row decoder to select one column of the memory array and execute sequential programming operations on a desired block of memory cells belonging to contiguous selected rows of the selected column.Type: ApplicationFiled: February 16, 2015Publication date: August 27, 2015Inventors: Antonino CONTE, Alberto Jose' DI MARTINO, Kailash KHAIRNAR
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Patent number: 8385135Abstract: A voltage regulator for a regulated voltage generator configured to generate an operating voltage and including a variable comparison voltage generator, a comparison voltage, a partition branch including a plurality of active devices of a resistive type to receive the operating voltage and supply an intermediate voltage correlated to the operating voltage, and a comparator, to receive the comparison voltage and the intermediate voltage and supply a regulation signal for the regulated-voltage generator.Type: GrantFiled: September 14, 2010Date of Patent: February 26, 2013Assignee: STMicroelectronics S.r.l.Inventors: Antonino Conte, Alberto Jose Di Martino, Enrico Castaldo
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Publication number: 20110069562Abstract: A voltage regulator for a regulated voltage generator configured to generate an operating voltage and including a variable comparison voltage generator, a comparison voltage, a partition branch including a plurality of active devices of a resistive type to receive the operating voltage and supply an intermediate voltage correlated to the operating voltage, and a comparator, to receive the comparison voltage and the intermediate voltage and supply a regulation signal for the regulated-voltage generator.Type: ApplicationFiled: September 14, 2010Publication date: March 24, 2011Applicant: STMICROELECTRONICS S.R.L.Inventors: Antonino Conte, Alberto Jose Di Martino, Enrico Castaldo
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Patent number: 7551041Abstract: An oscillator is provided that includes at least one capacitor, at least one comparator, and at least one device for charging or discharging the at least one capacitor. The capacitor is coupled to the comparator. The comparator compares the voltage on the capacitor with a reference voltage, and activates the device so as to command the charging or the discharging of the capacitor. The oscillator also comprises a circuit for supplying a preset voltage to the comparator when the device commands the charging of the capacitor, so that the comparator compares the reference voltage diminished by the preset voltage with the voltage on the capacitor, or the voltage on the capacitor added to the preset voltage with the reference voltage.Type: GrantFiled: October 28, 2005Date of Patent: June 23, 2009Assignee: STMicroelectronics s.r.l.Inventors: Antonino Conte, Alberto Josè Di Martino
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Patent number: 7321516Abstract: A biasing structure for a memory cell storage element, for setting an operating voltage at an accession electrode of the memory cell storage element. The biasing structure includes a biasing transistor coupled to the accession electrode and adapted to set the operating voltage based on a biasing voltage received at a control electrode of the biasing transistor, and a biasing voltage generator for generating the biasing voltage. The biasing voltage generator includes a feedback voltage regulation structure adapted track changes in a threshold voltage of the biasing transistor, so as to keep the operating voltage at the accession electrode of the memory cell storage element substantially stable against operating condition changes.Type: GrantFiled: February 22, 2005Date of Patent: January 22, 2008Assignee: STMicroelectronics, S.r.l.Inventors: Alberto Jose' Di Martino, Enrico Castaldo, Nicolas Demange, Daniele Salvatore Zompi
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Patent number: 7130219Abstract: A memory device formed by an array of memory cells extending in rows and columns. The device is formed by a plurality of N-type wells extending parallel to the rows; each N-type well houses a plurality of P-type wells extending in a direction transverse to the rows. A plurality of main bitlines extend along the columns. Each P-type well is associated to a set of local bitlines that extend along the respective P-type well and are coupled to the drain terminals of the cells accommodated in the respective P-type well. Local-bitlines managing circuits are provided for each P-type well and are located between the main bitlines and a respective set of local bitlines for controllably connecting each local bitline to a respective main bitline.Type: GrantFiled: February 25, 2005Date of Patent: October 31, 2006Assignee: STMicroelectronics S.r.l.Inventors: Antonino Conte, Mario Micciche′, Alberto José Di Martino, Alfredo Signorello