Patents by Inventor Alberto Martinez-Limia

Alberto Martinez-Limia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230402538
    Abstract: A vertical semiconductor component. The component includes: a drift region having a first conductivity type; a trench structure on or above the drift region, a shielding structure situated laterally next to at least one sidewall of the trench structure on or above the drift region and having a second conductivity type, and the shielding structure having at least a part of a shielding structure-trench structure such that the shielding structure has at least a first region having a first thickness and a second region having a second thickness, and an edge termination structure on or above the drift region and having the second conductivity type, and the shielding structure having a first doping degree, and the edge termination structure having a second doping degree; and at least in the second region of the shielding structure, the edge termination structure being situated between the drift region and the shielding structure.
    Type: Application
    Filed: November 17, 2021
    Publication date: December 14, 2023
    Inventors: Alberto Martinez-Limia, Daniel Krebs, Stephan Schwaiger, Wolfgang Feiler
  • Publication number: 20230118158
    Abstract: A vertical fin field-effect transistor. The transistor has a semiconductor fin, an n-doped source region, an n-doped drift region, an n-doped channel region in the semiconductor fin situated vertically between the source region and the drift region, a gate region horizontally adjacent to the channel region, a gate dielectric electrically insulating the gate region from the channel region, a boundary surface between the gate dielectric and the channel region having negative boundary surface charges, a p-doped gate shielding region situated below the gate region so that, given the vertical projection, the gate shielding region is situated within a surface limited by the gate dielectric, a source contact electrically conductively connected to the source region, and an electrically conductive region between the gate region and the p-doped gate shielding region. The p-doped gate shielding region is electrically conductively connected to the source contact by the electrically conductive region.
    Type: Application
    Filed: February 15, 2021
    Publication date: April 20, 2023
    Inventors: Daniel Krebs, Joachim Rudhard, Alberto Martinez-Limia, Jens Baringhaus, Wolfgang Feiler
  • Publication number: 20220320286
    Abstract: A power transistor cell including a layer arrangement, which includes a front side and a rear side, the front side being situated opposite the rear side. A trench extends starting from, and perpendicular to, the front side along a first direction into the layer arrangement. The trench extends at least into a current-spreading layer, and expands along a second direction, which is situated perpendicularly to the first direction. Field shielding areas are situated at least partially in the current-spreading layer, wherein source areas and field shielding contacting areas are situated alternatingly along the second direction. One portion each of the body areas is situated between each source area and each field shielding contacting area. The field shielding contacting areas connect the field shielding areas to first metal areas on the front side. The field shielding contacting areas make contact at least partially with side faces of the trench.
    Type: Application
    Filed: May 18, 2020
    Publication date: October 6, 2022
    Inventors: Alberto Martinez-Limia, Jan-Hendrik Alsmeier, Klaus Heyers, Stephan Schwaiger, Wolfgang Feiler
  • Publication number: 20220246754
    Abstract: A semiconductor device. The semiconductor device includes a drift region of a first conductivity type, a channel region of a second conductivity type on the drift region, a source region of the first conductivity type on the channel region, a trench, which forms an insulated gate and extends through the source region and the channel region so that its bottom is situated in the drift region, and at least one buried region of the second conductivity type, which extends within the drift region from an edge region of the drift region to the trench and is in direct contact with a first subarea of a surface of the trench, a second subarea of a surface of the trench being in direct contact with the drift region, and the buried region being connected to the source region in an electrically conducting manner.
    Type: Application
    Filed: August 19, 2020
    Publication date: August 4, 2022
    Inventors: Alberto Martinez-Limia, Jan-Hendrik Alsmeier, Klaus Heyers, Stephan Schwaiger, Wolfgang Feiler
  • Publication number: 20220231148
    Abstract: A method for manufacturing a power transistor. The method includes: applying a first epitaxial layer including a first doping concentration to a front side of a semiconductor substrate, producing an expansion layer, which is situated inside the first epitaxial layer, producing various implanted areas starting from the front side of the semiconductor substrate, producing a trench structure starting from the front side of the semiconductor substrate, producing first isolation areas in the surroundings of the trench structure, producing transistor heads, and applying metal layers.
    Type: Application
    Filed: May 26, 2020
    Publication date: July 21, 2022
    Inventors: Alberto Martinez-Limia, Franziska Felicitas Fink, Jan-Hendrik Alsmeier, Stephan Schwaiger, Wolfgang Feiler
  • Publication number: 20220231120
    Abstract: A transistor cell including a semiconductor substrate, which has a front side and a rear side, the front side being situated opposite the rear side. An epitaxial layer is situated on the front side. Channel regions are situated on the epitaxial layer. Source regions are situated on the channel regions. A trench and field shielding regions extending from the front side of the semiconductor substrate into the epitaxial layer, the field shielding regions each being situated laterally spaced apart from the trench and the trench having a shallower depth than the field shielding regions. An implanted expansion region having a particular thickness is situated below the trench.
    Type: Application
    Filed: May 18, 2020
    Publication date: July 21, 2022
    Inventors: Alberto Martinez-Limia, Stephan Schwaiger, Daniel Krebs, Dick Scholten, Holger Bartolf, Jan-Hendrik Alsmeier, Wolfgang Feiler
  • Publication number: 20220209006
    Abstract: A semiconductor component. The semiconductor component includes a semiconductor substrate that includes a first side, on which an epitaxial layer is situated. On the epitaxial layer, body regions are sectionally situated, and on the body regions, source regions are situated. A plurality of first trenches and a plurality of second trenches extending starting from the source regions into the epitaxial layer. The first trenches have a greater depth than the second trenches. A second trench sectionally extends into a first trench in each case. On a trench surface of the first trenches, a layer including a first doping is situated in each case. The first trenches are filled with a first material including a second doping, the first doping having a higher value than the second doping.
    Type: Application
    Filed: March 25, 2020
    Publication date: June 30, 2022
    Inventors: Alberto Martinez-Limia, Alfred Goerlach, Holger Bartolf, Stephan Schwaiger, Wolfgang Feiler
  • Publication number: 20210005711
    Abstract: A vertical power transistor, including a semiconductor substrate, on which at least one first layer and one second layer are situated, the second layer being situated on the first layer, and the first layer including a first semiconductor material; and a plurality of trenches, which extend from an upper side of the second layer into the first layer. The first layer has a first doping, and each trench has a first region, which extends from the respective trench bottom to a first level. Each first region is filled with a second semiconductor material, which has a second doping. The first semiconductor material and the second semiconductor material are different. Each first region is connected electrically to the second layer. The second doping is higher than the first doping. Heterojunctions, which behave as unipolar, rectifying junctions, form between the first layer and each first region.
    Type: Application
    Filed: November 19, 2018
    Publication date: January 7, 2021
    Inventors: Alberto Martinez-Limia, Alfred Goerlach, Holger Bartolf, Stephan Schwaiger, Wolfgang Feiler
  • Publication number: 20150093285
    Abstract: The present invention relates to a magnetic material, which contains at least one transition metal (TM), at least one rare earth metal (RE) and tungsten, wherein the proportion of transition metal (TM) is 60 to 90% by mass, the proportion of rare earth metal (RE) is 10 to 20% by mass, and the proportion of tungsten (W) is 5 to 25% by mass, in each case in relation to the total mass of the magnetic material.
    Type: Application
    Filed: April 19, 2013
    Publication date: April 2, 2015
    Inventors: Stefan Hinderberger, Christian Wegierski, Peter Barth, Gerhard Schneider, Arne Huber, Juergen Oberle, Dagmar Goll, Friederike Koeppen, Lars Bommer, Roland Stein, Markus Raith, Alberto Martinez-Limia, Roman Karimi, Ingrid Wuehrl, T-akashi Shigematsu