Abstract: In various embodiments, techniques can be provided to address debug efficiency for failures found on an operational system. The techniques can utilize a real-time trigger to notify a memory device to dump an error log to timely capture all needed information. In response to detecting one or more error conditions associated with the memory device, a system that interfaces with the memory device can generate a trigger signal to the memory device. In response to identifying the trigger signal, the memory device can dump an error log of the memory device to a memory component in the memory device. The error log can later be retrieved from the memory component for failure analysis.

Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.

Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.

Abstract: Methods, systems, and devices for read disturb management for memory are described. In some instances, data may be read from a first page of a virtual block of a memory system. If the data includes one or more errors, the memory system may read data from a second page of the virtual block and determine whether one or more errors exist in the data. The memory system may continue reading pages of the virtual block until a page includes no (or relatively few errors). The memory system may then refresh the pages.

Abstract: Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.

Abstract: Methods, systems, and devices for data relocation operation techniques are described. A memory system may include blocks of memory cells, for example, within a non-volatile memory device of the memory system. The memory system may identify a command to perform a data relocation operation associated with a block of memory cells and may select between a first procedure and a second procedure for performing the data relocation operation. The memory system may select between the first procedure and the second procedure based on whether one or more parameters associated with the data relocation operation satisfy a threshold. For example, the memory system may select the first procedure if the one or more parameters satisfy the threshold and may select the second procedure if the one or more parameters do not satisfy the threshold. The memory system may perform the data relocation operation using the selected procedure.

Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.

Abstract: Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.

Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.

Abstract: Methods, systems, and devices for improved data management for memory are described. An apparatus may include a memory array including one or more blocks of memory cells. Data read from a block of memory cells may be written to a buffer, to support providing the data to a host system or modification of the data by the host system. If a quantity of read commands performed at the block of memory cells satisfies a threshold, the data may be written from the buffer to a different block of memory cells, rather than the block from which the data was previously read.

Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.

Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.

Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.

Abstract: Methods, systems, and devices for improved data management for memory are described. An apparatus may include a memory array including one or more blocks of memory cells. Data read from a block of memory cells may be written to a buffer, to support providing the data to a host system or modification of the data by the host system. If a quantity of read commands performed at the block of memory cells satisfies a threshold, the data may be written from the buffer to a different block of memory cells, rather than the block from which the data was previously read.

Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.

Abstract: Methods, systems, and devices for data relocation operation techniques are described. A memory system may include blocks of memory cells, for example, within a non-volatile memory device of the memory system. The memory system may identify a command to perform a data relocation operation associated with a block of memory cells and may select between a first procedure and a second procedure for performing the data relocation operation. The memory system may select between the first procedure and the second procedure based on whether one or more parameters associated with the data relocation operation satisfy a threshold. For example, the memory system may select the first procedure if the one or more parameters satisfy the threshold and may select the second procedure if the one or more parameters do not satisfy the threshold. The memory system may perform the data relocation operation using the selected procedure.

Abstract: In various embodiments, techniques can be provided to address debug efficiency for failures found on an operational system. The techniques can utilize a real-time trigger to notify a memory device to dump an error log to timely capture all needed information. In response to detecting one or more error conditions associated with the memory device, a system that interfaces with the memory device can generate a trigger signal to the memory device. In response to identifying the trigger signal, the memory device can dump an error log of the memory device to a memory component in the memory device. The error log can later be retrieved from the memory component for failure analysis.

Abstract: In various embodiments, techniques can be provided to address debug efficiency for failures found on an operational system. The techniques can utilize a real-time trigger to notify a memory device to dump an error log to timely capture all needed information. In response to detecting one or more error conditions associated with the memory device, a system that interfaces with the memory device can generate a trigger signal to the memory device. In response to identifying the trigger signal, the memory device can dump an error log of the memory device to a memory component in the memory device. The error log can later be retrieved from the memory component for failure analysis.

Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.

Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.