Patents by Inventor Alberto Scandurra
Alberto Scandurra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9105316Abstract: A package includes a first die and a second die. An interface connects the first die and the second die. At least one of the first and second dies includes a memory. The interface is configured to transport both control signals and memory transactions. A multiplexing circuit multiplexes the control signals and the memory transactions onto the interface such that connections of the interface are shared by the control signals and the memory transactions.Type: GrantFiled: December 10, 2013Date of Patent: August 11, 2015Assignees: STMicroelectronics (Research & Development) Limited, STMicroelectronics S.r.l.Inventors: Andrew Michael Jones, Stuart Ryan, Alberto Scandurra
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Patent number: 8948215Abstract: A deserializer circuit includes demultiplexer circuitry configured to receive serial data from an input and output a plurality of divided data outputs, and multiplexer circuitry configured to receive a first logic level at a first input of said multiplexer circuitry, and receive a second logic level at a second input of said multiplexer circuitry and receive one of said divided data outputs at a control input of said multiplexer circuitry. The outputs of the multiplexer circuitry produce the received serial data in a parallel form.Type: GrantFiled: April 18, 2012Date of Patent: February 3, 2015Assignees: STMicroelectronics SA, STMicroelectronics S.r.l.Inventors: Mounir Zid, Alberto Scandurra, Carmelo Pistritto, Rached Tourki
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Publication number: 20140098617Abstract: A package includes a first die and a second die. An interface connects the first die and the second die. At least one of the first and second dies includes a memory. The interface is configured to transport both control signals and memory transactions. A multiplexing circuit multiplexes the control signals and the memory transactions onto the interface such that connections of the interface are shared by the control signals and the memory transactions.Type: ApplicationFiled: December 10, 2013Publication date: April 10, 2014Applicants: STMicroelectronics S.r.l., STMicroelectronics (Research & Development) LimitedInventors: Andrew Michael Jones, Stuart Ryan, Alberto Scandurra
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Patent number: 8629544Abstract: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A multiplexer is provided to multiplex the control signals and memory transactions onto the interface such that a plurality of connections of said interface are shared by the control signals and the memory transactions.Type: GrantFiled: December 2, 2010Date of Patent: January 14, 2014Assignees: STMicroelectronics (Research & Development) Limited, STMicroelectronics S.r.l.Inventors: Andrew Michael Jones, Stuart Ryan, Alberto Scandurra
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Patent number: 8610258Abstract: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A sampling circuit samples the control signals before transport on the interface. The sampling circuit is controlled in dependence on at least one quality of service parameter associated with a respective control signal.Type: GrantFiled: December 2, 2010Date of Patent: December 17, 2013Assignees: STMicroelectronics (Research & Development) Limited, STMicroelectronics S.r.l.Inventors: Andrew Michael Jones, Stuart Ryan, Alberto Scandurra
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Patent number: 8576879Abstract: A communication system for transmitting data, for example, within a System-in-Package. The system includes a first circuit configured for: a) dividing the data into a plurality of packets having a determined size; and b) creating for each of the packets a transmission segment including a segment header and the respective packet as payload. The system also includes a second circuit configured for: a) separating the transmission segments into a plurality of physical units, where the physical units have a determined size; and b) transmitting the physical units over a physical communication channel. In particular, the segment header includes at least one field that identifies the number of physical units that are to be transmitted.Type: GrantFiled: May 27, 2011Date of Patent: November 5, 2013Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics S.r.l.Inventors: Alberto Scandurra, Giuseppe Guarnaccia, Ignazio Antonino Urzi'
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Patent number: 8570069Abstract: A clock gate includes a first Muller gate that receives at its inputs a clock signal and an enable signal. The output of the first Muller gate is applied, with a delayed version of the clock signal, to a second Muller gate. A logic circuit operates to logically combine the output of the second Muller gate with a delayed version of the clock signal. The output of the logic circuit provides a gated clock output.Type: GrantFiled: April 19, 2012Date of Patent: October 29, 2013Assignees: STMicroelectronics S.A., STMicroelectronics S.r.l.Inventors: Mounir Zid, Alberto Scandurra
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Patent number: 8538273Abstract: A system for exchanging information in an on-chip communication network using optical flow information for communication between Intellectual Property cores. The information is exchanged between a plurality of initiators and targets in the Intellectual Property cores. The system includes a router for propagating optical flow information from the initiators to the targets. Each initiator includes an interface to convert the traffic generated by the initiator and transmit it in the form of an optical flow within the on-chip communication network, and each target includes an interface to convert information from the optical form into the electrical form. The system is organized as a parametric system and includes programming module to define a first set of high level parameters, a second set of initiator network interface parameters and a third set of target network interface parameters.Type: GrantFiled: July 26, 2012Date of Patent: September 17, 2013Assignee: STMicroelectronics s.r.l.Inventors: Alberto Scandurra, Giovanni Strano, Carmelo Pistritto
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Patent number: 8401404Abstract: An on-chip receiver for flows of information conveyed to a target via optical signals with different wavelengths includes a plurality of photo-detector modules, each sensitive to a different wavelength, for converting a respective optical signal at input into an electrical signal, a plurality of de-serialization circuits acting on the electrical signals for converting into packet traffic the flows of information received via the photo-detector modules, and an arbitration node acting on the packet traffic to enable a single packet at a time to achieve the target.Type: GrantFiled: May 28, 2010Date of Patent: March 19, 2013Assignee: STMicroelectronics S.r.l.Inventors: Alberto Scandurra, Giuseppe Guarnaccia, Salvatore Pisasale, Fabio Zito
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Patent number: 8401388Abstract: A transmitter for generating, starting from a data-packet traffic at input, flows of information to be conveyed via optical signals with different wavelengths towards a plurality of targets in a communications network, the transmitter including: a destination decoder to identify, for each packet in the input packet traffic, a respective destination target in the plurality of targets; a plurality of emitter modules operating at different wavelengths for converting the electrical signals into optical signals; and a de-multiplexer, which is controlled by the destination decoder and is able to drive the emitter modules by sending selectively to each emitter module the electrical signals corresponding to a given packet of the input packet traffic according to the respective destination target identified by the destination decoder. A serialization module is set upstream of the de-multiplexer for converting the packet traffic into a serial flow of bits.Type: GrantFiled: May 28, 2010Date of Patent: March 19, 2013Assignee: STMicroelectronics S.r.l.Inventors: Alberto Scandurra, Mirko Dondini, Salvatore Pisasale, Letizia Fragomeni
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Publication number: 20120301144Abstract: A system for exchanging information in an on-chip communication network using optical flow information for communication between Intellectual Property cores. The information is exchanged between a plurality of initiators and targets in the Intellectual Property cores. The system includes a router for propagating optical flow information from the initiators to the targets. Each initiator includes an interface to convert the traffic generated by the initiator and transmit it in the form of an optical flow within the on-chip communication network, and each target includes an interface to convert information from the optical form into the electrical form. The system is organized as a parametric system and includes programming module to define a first set of high level parameters, a second set of initiator network interface parameters and a third set of target network interface parameters.Type: ApplicationFiled: July 26, 2012Publication date: November 29, 2012Applicant: STMicroelectronics s.r.l.Inventors: Alberto Scandurra, Giovanni Strano, Carmelo Pistritto
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Publication number: 20120268168Abstract: A clock gate includes a first Muller gate that receives at its inputs a clock signal and an enable signal. The output of the first Muller gate is applied, with a delayed version of the clock signal, to a second Muller gate. A logic circuit operates to logically combine the output of the second Muller gate with a delayed version of the clock signal. The output of the logic circuit provides a gated clock output.Type: ApplicationFiled: April 19, 2012Publication date: October 25, 2012Applicants: STMICROELECTRONICS SRL, STMICROELECTRONICS S.A.Inventors: Mounir Zid, Alberto Scandurra
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Publication number: 20120269206Abstract: A deserializer circuit includes demultiplexer circuitry configured to receive serial data from an input and output a plurality of divided data outputs, and multiplexer circuitry configured to receive a first logic level at a first input of said multiplexer circuitry, and receive a second logic level at a second input of said multiplexer circuitry and receive one of said divided data outputs at a control input of said multiplexer circuitry. The outputs of the multiplexer circuitry produce the received serial data in a parallel form.Type: ApplicationFiled: April 18, 2012Publication date: October 25, 2012Applicants: STMICROELECTRONICS S.A., UNIVERSITE DE MONASTIR, STMICROELECTRONICS SRLInventors: Mounir Zid, Alberto Scandurra, Carmelo Pistritto, Rached Tourki
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Patent number: 8260147Abstract: A system for exchanging information in an on-chip communication network using optical flow information for communication between Intellectual Property cores. The information is exchanged between a plurality of initiators and targets in the Intellectual Property cores. The system includes a router for propagating optical flow information from the initiators to the targets. Each initiator includes an interface to convert the traffic generated by the initiator and transmit it in the form of an optical flow within the on-chip communication network, and each target includes an interface to convert information from the optical form into the electrical form. The system is organized as a parametric system and includes programming module to define a first set of high level parameters, a second set of initiator network interface parameters and a third set of target network interface parameters.Type: GrantFiled: April 9, 2010Date of Patent: September 4, 2012Assignee: STMicroelectronics S.r.l.Inventors: Alberto Scandurra, Giovanni Strano, Carmelo Pistritto
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Patent number: 8199751Abstract: A method of performing transactions in a communication network in which is exchanged between Intellectual Property (IP) cores has information transported in packets which include a header for transporting control information and one or more payloads transporting content. A versatile packet format is used which is adapted to transport different traffic patterns generated by the IP cores using different protocols for simple interoperability between the IP cores and also providing configurability of the granularity arbitration process to correct crossing the routers in the communication network.Type: GrantFiled: September 25, 2009Date of Patent: June 12, 2012Assignee: STMicroelectronics s.r.l.Inventors: Alberto Scandurra, Giuseppe Falconeri, Daniele Mangano
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Publication number: 20110320669Abstract: A communication system for transmitting data, for example, within a System-in-Package. The system includes a first circuit configured for: a) dividing the data into a plurality of packets having a determined size; and b) creating for each of the packets a transmission segment including a segment header and the respective packet as payload. The system also includes a second circuit configured for: a) separating the transmission segments into a plurality of physical units, where the physical units have a determined size; and b) transmitting the physical units over a physical communication channel. In particular, the segment header includes at least one field that identifies the number of physical units that are to be transmitted.Type: ApplicationFiled: May 27, 2011Publication date: December 29, 2011Applicants: STMICROELECTRONICS S.R.L., STMICROELECTRONICS (GRENOBLE 2) SASInventors: Alberto Scandurra, Giuseppe Guarnaccia, Ignazio Antonino Urzi'
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Publication number: 20110134705Abstract: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A multiplexer is provided to multiplex the control signals and memory transactions onto the interface such that a plurality of connections of said interface are shared by the control signals and the memory transactions.Type: ApplicationFiled: December 2, 2010Publication date: June 9, 2011Applicants: STMICROELECTRONICS (R&D) LTD, STMICROELECTRONICS SRLInventors: Andrew Michael Jones, Stuart Ryan, Alberto Scandurra
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Publication number: 20110133825Abstract: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A sampling circuit samples the control signals before transport on the interface. The sampling circuit is controlled in dependence on at least one quality of service parameter associated with a respective control signal.Type: ApplicationFiled: December 2, 2010Publication date: June 9, 2011Applicants: STMICROELECTRONICS (R&D) LTD, STMICROELECTRONICS S.R.L.Inventors: Andrew Michael Jones, Stuart Ryan, Alberto Scandurra
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Publication number: 20100322625Abstract: A transmitter for generating, starting from a data-packet traffic at input, flows of information to be conveyed via optical signals with different wavelengths towards a plurality of targets in a communications network, the transmitter including: a destination decoder to identify, for each packet in the input packet traffic, a respective destination target in the plurality of targets; a plurality of emitter modules operating at different wavelengths for converting the electrical signals into optical signals; and a de-multiplexer, which is controlled by the destination decoder and is able to drive the emitter modules by sending selectively to each emitter module the electrical signals corresponding to a given packet of the input packet traffic according to the respective destination target identified by the destination decoder. A serialization module is set upstream of the de-multiplexer for converting the packet traffic into a serial flow of bits.Type: ApplicationFiled: May 28, 2010Publication date: December 23, 2010Applicant: STMICROELECTRONICS S.R.L.Inventors: Alberto Scandurra, Mirko Dondini, Salvatore Pisasale, Letizia Fragomeni
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Publication number: 20100322638Abstract: An on-chip receiver for flows of information conveyed to a target via optical signals with different wavelengths includes a plurality of photo-detector modules, each sensitive to a different wavelength, for converting a respective optical signal at input into an electrical signal, a plurality of de-serialization circuits acting on the electrical signals for converting into packet traffic the flows of information received via the photo-detector modules, and an arbitration node acting on the packet traffic to enable a single packet at a time to achieve the target.Type: ApplicationFiled: May 28, 2010Publication date: December 23, 2010Applicant: STMicroelectronics S.r.I.Inventors: Alberto Scandurra, Giuseppe Guarnaccia, Salvatore Pisasale, Fabio Zito