Patents by Inventor Albertus Theodorus Maria Van De Goor

Albertus Theodorus Maria Van De Goor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6797615
    Abstract: A method of manufacturing a semiconductor device, in which a surface (1) of a semiconductor body (2) is provided with a first metallization layer comprising conductor tracks (3, 4), among which a number having a width w an a number having a greater width. On this structure an insulating layer (5) is deposited by means of a process in which the thickness of the formed insulating layer (5) is dependent on the width of the subjacent conductor tracks (3, 4), after which a capping layer (6) is deposited on the insulating layer (5). Then the silicon oxide layer is planarized by means of a polishing process. In this method, the conductor tracks having a width greater than w are split up into a number of parallel strips (10) having a width w, which strips are locally connected to one another.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: September 28, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Erik Jan Lous, Albertus Theodorus Maria Van De Goor, Anco Heringa
  • Patent number: 6605824
    Abstract: The invention relates to a semiconductor device comprising a bond pad structure, which bond pad structure enables analyses to be carried out at a level of a metal layer of the semiconductor device and comprises a matrix comprising trenches filled with a conductive material, which matrix is electrically contacted by the metal layer.
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: August 12, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Albertus Theodorus Maria Van De Goor
  • Patent number: 6555470
    Abstract: Method of making a semiconductor device, in which method a first layer of silicon oxide (10) is deposited on a surface (2) of a silicon body (1), which layer is then provided with contact windows (11) within which semiconductor zones (5) formed in body and conductor tracks (6) of non-crystalline silicon formed on the surface are exposed. On the first layer of silicon oxide a first metallization layer is formed, comprising conductor tracks (16) which are in contact with the semiconductor zones (5) and conductor tracks (6) within the contact windows (11). The first metallization is then covered with a second layer of silicon oxide (17) which is provided with contact windows (19) within which the conductor tracks (16) of the first metallization are exposed. Then, successively, an adhesion layer (20) is deposited, the contact windows (19) are filled with tungsten plugs (22), and a second metallization layer is formed comprising conductor tracks in contact with the tungsten plugs.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: April 29, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Albertus Theodorus Maria Van De Goor
  • Publication number: 20020155651
    Abstract: Method of making a semiconductor device, in which method a first layer of silicon oxide (10) is deposited on a surface (2) of a silicon body (1), which layer is then provided with contact windows (11) within which semiconductor zones (5) formed in body and conductor tracks (6) of non-crystalline silicon formed on the surface are exposed. On the first layer of silicon oxide a first metallization layer is formed, comprising conductor tracks (16) which are in contact with the semiconductor zones (5) and conductor tracks (6) within the contact windows (11). The first metallization is then covered with a second layer of silicon oxide (17) which is provided with contact windows (19) within which the conductor tracks (16) of the first metallization are exposed. Then, successively, an adhesion layer (20) is deposited, the contact windows (19) are filled with tungsten plugs (22), and a second metallization layer is formed comprising conductor tracks in contact with the tungsten plugs.
    Type: Application
    Filed: March 19, 2002
    Publication date: October 24, 2002
    Inventor: Albertus Theodorus Maria Van De Goor
  • Publication number: 20010048105
    Abstract: The invention relates to a semiconductor device comprising a bond pad structure, which bond pad structure enables analyses to be carried out at a level of a metal layer of the semiconductor device and comprises a matrix comprising trenches filled with a conductive material, which matrix is electrically contacted by the metal layer.
    Type: Application
    Filed: April 10, 2001
    Publication date: December 6, 2001
    Inventor: Albertus Theodorus Maria Van De Goor