Patents by Inventor Albrecht Mayer
Albrecht Mayer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12339975Abstract: A device includes a safety domain having a processing unit and a memory and is configured to provide at least one functionality and to implement one more safety measures for detecting faults. The safety domain is configured to transmit at least one alarm signal indicating one or more detected errors in response to detecting the faults. The device further includes a security domain having a processing unit and a memory and is configured to provide cryptographic services and to obtain alarm signals. The security domain is configured to perform security-related operations in a secure state in response to obtaining an alarm signal from the safety domain.Type: GrantFiled: March 22, 2022Date of Patent: June 24, 2025Assignee: Infineon Technologies AGInventors: Joerg Syassen, Avni Bildhaiya, Andreas Graefe, Albrecht Mayer, Manuela Meier, Viola Rieger
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Patent number: 12326831Abstract: In various examples, a system on a chip is provided that is configured to be operated in a debug mode. The system on a chip includes a plurality of processor cores including a plurality of virtual machines and a further processor core, configured to, in the debug mode, initially execute first debug instructions after the system on a chip has started operating. The first debug instructions are configured to cause the further processor core to make a debug setting that, after the first debug instructions are executed, prevents a processor core executing second debug instructions from accessing at least one of the virtual machines and allows the processor core executing the second debug instructions to access at least one other of the virtual machines.Type: GrantFiled: February 24, 2022Date of Patent: June 10, 2025Assignee: Infineon Technologies AGInventors: Albrecht Mayer, Patrik Eder, Kajetan Nuernberger
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Patent number: 12287862Abstract: A semiconductor chip includes an electronic hardware circuitry device that includes a plurality of partitionable hardware resources that each includes a corresponding resource allocation state. The electronic hardware circuitry includes a logic control circuit to control access to the plurality of hardware resources based on the respective resource allocation states of the hardware resources and based on input from one or more authorized agents. The semiconductor chip further includes a processor core to implement a plurality of software applications belonging to a first group or to a second group, each of the plurality of applications configured to access and interact with at least one corresponding hardware resource assigned to the respective application, implement assigning software agents each authorized and configured to cause the electronic hardware circuitry device to assign one or more unassigned hardware resources only to one or more of the software applications belonging to certain groups.Type: GrantFiled: November 7, 2022Date of Patent: April 29, 2025Assignee: Infineon Technologies AGInventors: Sandeep Vangipuram, Glenn Farrall, Albrecht Mayer, Frank Hellwig
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Publication number: 20240411667Abstract: A system and method for tracing a cyclic program execution of a processing circuit of an integrated circuit. A trace unit of the integrated circuit captures trace snippets during respective occurrences of a hyper-period of the cyclic program execution of the processing circuit. A trace buffer of the integrated circuit stores the trace snippets. A processor, which is coupled to the integrated circuit, reconstructs the hyper-period by combining overlapping portions of the trace snippets from the trace buffer.Type: ApplicationFiled: May 14, 2024Publication date: December 12, 2024Inventors: Albrecht Mayer, Ibai Irigoyen Ceberio, Gasper Skvarc Bozic
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Publication number: 20240403497Abstract: Systems, methods, and circuitries are disclosed for providing security for tool access in a device. In one example, a device includes a bus master, a memory protection unit, and protection agent circuitry. The bus master is configured to store, in a first range of memory locations, request messages received from a tool interface of the device, each request message encapsulating a tool-related command. The memory protection unit is configured to prevent the bus master from accessing memory locations outside of the first range of memory locations. The protection agent circuitry is configured to access the first range of memory locations to identify one or more request messages, and send each respective request message to one of a plurality of component circuitries based on a component circuitry identified by the request message.Type: ApplicationFiled: June 2, 2023Publication date: December 5, 2024Inventors: Albrecht Mayer, Gasper Skvarc Bozic
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Publication number: 20240322499Abstract: A circuit is disclosed having one or more circuits, a connector portion coupled to the one or more circuits, and comprising a plurality of pins. When the connector portion is coupled with a first connector in a first orientation, the one or more circuits are configured to operate in a first state, and when the connector portion is coupled with the first connector in a second orientation, at least one pin of the plurality of pins receives a signal causing the one or more circuits to operate in a second state different from the first state. The second orientation being different from the first orientation.Type: ApplicationFiled: June 4, 2024Publication date: September 26, 2024Inventors: Albrecht Mayer, Patrik Eder
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Patent number: 12034256Abstract: A circuitry is disclosed having one or more circuits and a connector portion coupled that is to the one or more circuits. The connector portion includes a plurality of pins, at least some of the pins having assigned functionality, and wherein at least one first pin is to activate a mechanism to bring the one or more circuits into an electrically safe state. The circuitry is configured, in case the connector portion is coupled with a first connector in a first orientation, to allow the one or more circuits to operate properly via the connector portion. The circuitry is also configured so that in a case where the connector portion is coupled with a second connector in a second orientation different from the first orientation, the at least one first pin of the plurality of pins receives a reference potential that triggers activation of a safety mechanism.Type: GrantFiled: May 25, 2021Date of Patent: July 9, 2024Assignee: Infineon Technologies AGInventors: Albrecht Mayer, Patrik Eder
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Publication number: 20230401341Abstract: A non-volatile memory (NVM) system external to a processor comprising an NVM and a memory controller may perform various aspects of the techniques. The NVM may store a first cryptographic signature and first data. The memory controller may, responsive to a first write request to write updated data to at least a portion of the NVM, to store the updated data in the NVM along with the first data to create second data. The memory controller may also generate, a second cryptographic signature that always differs from the first cryptographic signature, and store the second cryptographic signature as a current cryptographic signature. The memory controller may further output, to the processor, the current cryptographic signature as a reference signature, where the memory controller always replaces the current cryptographic signature, with cryptographic properties, whenever the NVM is written to and does not otherwise permit writing the current cryptographic signature.Type: ApplicationFiled: June 8, 2022Publication date: December 14, 2023Inventors: Albrecht Mayer, Joerg Syassen, Glenn Ashley Farrall, Manfred Zimmerman
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Patent number: 11789739Abstract: A method includes incrementing a counter with transmission of a process data from a first processor to a second processor, periodically decrementing the counter, if the counter is greater than a predetermined floor threshold value, wherein a period is a predetermined time interval; and stalling the first processor, if the counter is above a configurable load threshold value, so as to re-schedule the transmission of the process data from the first processor to the second processor.Type: GrantFiled: May 3, 2021Date of Patent: October 17, 2023Assignee: Infineon Technologies AGInventors: Albrecht Mayer, Glenn Ashley Farrall
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Publication number: 20230267094Abstract: In various examples, a system on a chip is provided that is configured to be operated in a debug mode. The system on a chip includes a plurality of processor cores including a plurality of virtual machines and a further processor core, configured to, in the debug mode, initially execute first debug instructions after the system on a chip has started operating. The first debug instructions are configured to cause the further processor core to make a debug setting that, after the first debug instructions are executed, prevents a processor core executing second debug instructions from accessing at least one of the virtual machines and allows the processor core executing the second debug instructions to access at least one other of the virtual machines.Type: ApplicationFiled: February 24, 2022Publication date: August 24, 2023Inventors: Albrecht Mayer, Patrik Eder, Kajetan Nuernberger
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Patent number: 11562079Abstract: In different example embodiments, a system-on-chip is provided.Type: GrantFiled: October 24, 2019Date of Patent: January 24, 2023Assignee: Infineon Technologies AGInventors: Albrecht Mayer, Reinhard Deml, Viola Rieger, Alexander Zeh
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Publication number: 20220309169Abstract: A device includes a safety domain having a processing unit and a memory and is configured to provide at least one functionality and to implement one more safety measures for detecting faults. The safety domain is configured to transmit at least one alarm signal indicating one or more detected errors in response to detecting the faults. The device further includes a security domain having a processing unit and a memory and is configured to provide cryptographic services and to obtain alarm signals. The security domain is configured to perform security-related operations in a secure state in response to obtaining an alarm signal from the safety domain.Type: ApplicationFiled: March 22, 2022Publication date: September 29, 2022Inventors: Joerg Syassen, Avni Bildhaiya, Andreas Graefe, Albrecht Mayer, Manuela Meier, Viola Rieger
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Patent number: 11424932Abstract: A communication device is described including a receiver configured to receive a message including message data and a message authentication code, a first register for storing a received message authentication code and a second register for storing a computed message authentication code. The device also includes a first processor configured to extract the message authentication code from the message and to store the message authentication code in the first register, a second processor configured to compute a message authentication code based on the message data and to store the computed message authentication code in the second register, and a comparing circuit configured to compare the contents of the first register and the second register and to provide a comparison result.Type: GrantFiled: June 26, 2020Date of Patent: August 23, 2022Assignee: Infineon Technologies AGInventors: Andreas Graefe, Laurent Heidt, Albrecht Mayer
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Patent number: 11301249Abstract: Handling an exception includes (i) executing a return from an exception; and (ii) executing a subsequent instruction with an additional functionality in case the additional functionality of the subsequent instruction can be triggered by a special instruction.Type: GrantFiled: November 8, 2019Date of Patent: April 12, 2022Assignee: Infineon Technologies AGInventors: Albrecht Mayer, Neil Stuart Hastie, Pawel Jewstafjew
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Patent number: 11288404Abstract: A System on Chip (SoC), including a plurality of processor cores including a secure master, which is configured to run security software, and a non-secure master, which is configured to run non-security software; a resource configured to be shared by the secure master and the non-secure master; and a state machine configured to protect the resource by allowing only the secure master to transition the resource to a particular state of the state machine, and allowing only the non-secure master to transition the resource to another particular state of the state machine.Type: GrantFiled: June 14, 2019Date of Patent: March 29, 2022Assignee: Infineon Technologies AGInventors: Albrecht Mayer, Glenn Ashley Farrall, Frank Hellwig
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Publication number: 20210367366Abstract: A circuitry is disclosed having one or more circuits and a connector portion coupled that is to the one or more circuits. The connector portion includes a plurality of pins, at least some of the pins having assigned functionality, and wherein at least one first pin is to activate a mechanism to bring the one or more circuits into an electrically safe state. The circuitry is configured, in case the connector portion is coupled with a first connector in a first orientation, to allow the one or more circuits to operate properly via the connector portion. The circuitry is also configured so that in a case where the connector portion is coupled with a second connector in a second orientation different from the first orientation, the at least one first pin of the plurality of pins receives a reference potential that triggers activation of a safety mechanism.Type: ApplicationFiled: May 25, 2021Publication date: November 25, 2021Inventors: Albrecht Mayer, Patrik Eder
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Publication number: 20210271483Abstract: A method includes incrementing a counter with transmission of a process data from a first processor to a second processor, periodically decrementing the counter, if the counter is greater than a predetermined floor threshold value, wherein a period is a predetermined time interval; and stalling the first processor, if the counter is above a configurable load threshold value, so as to re-schedule the transmission of the process data from the first processor to the second processor.Type: ApplicationFiled: May 3, 2021Publication date: September 2, 2021Inventors: Albrecht Mayer, Glenn Ashley Farrall
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Patent number: 10996956Abstract: A method includes incrementing a counter with transmission of a process data from a first processor to a second processor, periodically decrementing the counter, if the counter is greater than a predetermined floor threshold value, wherein a period is a predetermined time interval; and stalling the first processor, if the counter is above a configurable load threshold value, so as to re-schedule the transmission of the process data from the first processor to the second processor.Type: GrantFiled: April 4, 2018Date of Patent: May 4, 2021Assignee: Infineon Technologies AGInventors: Albrecht Mayer, Glenn Ashley Farrall
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Publication number: 20200412543Abstract: A communication device is described including a receiver configured to receive a message including message data and a message authentication code, a first register for storing a received message authentication code and a second register for storing a computed message authentication code. The device also includes a first processor configured to extract the message authentication code from the message and to store the message authentication code in the first register, a second processor configured to compute a message authentication code based on the message data and to store the computed message authentication code in the second register, and a comparing circuit configured to compare the contents of the first register and the second register and to provide a comparison result.Type: ApplicationFiled: June 26, 2020Publication date: December 31, 2020Inventors: Andreas Graefe, Laurent Heidt, Albrecht Mayer
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Patent number: 10872030Abstract: A method includes invoking a first instruction that, when executed by a first processor, causes the first processor to perform a first operation, and that, when executed by the first processor, causes a second processor to perform a second operation. The method further includes a second instruction that, when executed by the first processor, causes the first processor to perform the first operation while causing the second processor to perform a third operation or while leaving the second processor unaffected. A control system includes a first processor and a second processor, wherein the first processor is configured to execute a first instruction to perform a first operation, wherein the second processor is configured to perform a second operation when the first processor executes the first instruction.Type: GrantFiled: July 17, 2018Date of Patent: December 22, 2020Assignee: Infineon Technologies AGInventor: Albrecht Mayer