Abstract: This invention relates to a semiconductor memory element with two field effect transistors and an arrangement in which these elements are utilized. In accordance with the invention, a field effect transistor, transfer transistor T.sub.t is provided with a memory gate for the information memory, such memory gate being directly connected to a drain/source region of a second field effect transistor, the charging transistor T.sub.L, both transistors T.sub.t and T.sub.L are connected with the write line, the second electrode of transistor T.sub.t is led to the operating voltage U.sub.E, and the capacitors C2 and C2.sup.x are linked to the word line from the gates of transistors T.sub.t and T.sub.L, thus obtaining a memory unit of a higher degree of integration but unimpaired readability, exceeding heretofore known reading speed.