Patents by Inventor Aldo Bottelli
Aldo Bottelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9748001Abstract: Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data, although this may be done at a penalty of under programming for some bits, as is described further below. A self contained Built In Self Test (BIST) flow constructed to collect the bit information through a set of column tests is also described.Type: GrantFiled: April 3, 2014Date of Patent: August 29, 2017Assignee: SanDisk Technologies LLCInventors: Yan Li, Kwang-ho Kim, Frank Tsai, Aldo Bottelli
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Patent number: 9461655Abstract: A system, method and computer readable storage medium are disclosed for phase interpolator to generate a single phase output clock signal based on plurality of phase-shifted component clock signals and a digital user input control signal to be utilized in combination with a delay-locked loop circuit. In one embodiment, the phase interpolator utilizes a method of phase-traversing when generating the single phase output clock signal that prevents over- or undershooting of the desired target phase of the single phase output clock signal.Type: GrantFiled: June 20, 2013Date of Patent: October 4, 2016Assignee: Synopsys, Inc.Inventors: Charles W. Boecker, Alvin Wang, Aldo Bottelli, Chethan Rao
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Publication number: 20150326229Abstract: A system, method and computer readable storage medium are disclosed for phase interpolator to generate a single phase output clock signal based on plurality of phase-shifted component clock signals and a digital user input control signal to be utilized in combination with a delay-locked loop circuit. In one embodiment, the phase interpolator utilizes a method of phase-traversing when generating the single phase output clock signal that prevents over- or undershooting of the desired target phase of the single phase output clock signal.Type: ApplicationFiled: June 20, 2013Publication date: November 12, 2015Inventors: Charles W. BOECKER, Alvin WANG, Aldo BOTTELLI, Chethan RAO
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Patent number: 9148154Abstract: A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.Type: GrantFiled: March 31, 2014Date of Patent: September 29, 2015Assignee: MoSys, Inc.Inventors: Prashant Choudhary, Aldo Bottelli, Charles W Boecker
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Publication number: 20150263737Abstract: A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.Type: ApplicationFiled: March 31, 2014Publication date: September 17, 2015Applicant: MOSYS, INC.Inventors: Prashant Choudhary, Aldo Bottelli, Charles W. Boecker
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Publication number: 20150244381Abstract: A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.Type: ApplicationFiled: March 31, 2014Publication date: August 27, 2015Applicant: MoSys, Inc.Inventors: Prashant Choudhary, Aldo Bottelli, Charles W. Boecker
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Publication number: 20140218083Abstract: A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.Type: ApplicationFiled: March 31, 2014Publication date: August 7, 2014Applicant: MoSys, Inc.Inventors: Prashant Choudhary, Aldo Bottelli, Charles W. Boecker
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Publication number: 20140219023Abstract: Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data, although this may be done at a penalty of under programming for some bits, as is described further below. A self contained Built In Self Test (BIST) flow constructed to collect the bit information through a set of column tests is also described.Type: ApplicationFiled: April 3, 2014Publication date: August 7, 2014Applicant: SanDisk Technologies Inc.Inventors: Yan Li, Kwang-ho Kim, Frank Tsai, Aldo Bottelli
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Publication number: 20140210531Abstract: A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.Type: ApplicationFiled: March 31, 2014Publication date: July 31, 2014Applicant: MOSYS, INC.Inventors: Prashant Choudhary, Aldo Bottelli, Charles W. Boecker
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Patent number: 8711625Abstract: Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data.Type: GrantFiled: November 10, 2011Date of Patent: April 29, 2014Assignee: SanDisk Technologies Inc.Inventors: Yan Li, Kwang-Ho Kim, Frank W. Tsai, Aldo Bottelli
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Patent number: 8704570Abstract: A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.Type: GrantFiled: December 19, 2012Date of Patent: April 22, 2014Assignee: MoSys, Inc.Inventors: Aldo Bottelli, Prashant Choudhary, Charles W Boecker
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Publication number: 20130154698Abstract: A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.Type: ApplicationFiled: December 19, 2012Publication date: June 20, 2013Applicant: MoSys, IncInventors: Aldo Bottelli, Prashant Choudhary, Charles W. Boecker
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Publication number: 20120297245Abstract: Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data.Type: ApplicationFiled: November 10, 2011Publication date: November 22, 2012Inventors: Yan Li, Kwang-ho Kim, Frank W. Tsai, Aldo Bottelli
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Patent number: 7996736Abstract: A technique for identifying bad pages of storage elements in a memory device. A flag byte is provided for each page group of one or more pages which indicates whether the page group is healthy. Flag bytes of selected page groups also indicate whether larger sets of page groups are healthy, according to bit positions in the flag bytes. A bad page identification process includes reading the flag bytes with a selected granularity so that not all flag bytes are read. Optionally, a drill down process reads flag bytes for smaller sets of page groups when a larger set of page groups is identified as having at least one bad page. This allows the bad page groups to be identified and marked with greater specificity. Redundant copies of flag bytes may be stored in different locations of the memory device. A majority vote process assigns a value to each bit.Type: GrantFiled: March 9, 2009Date of Patent: August 9, 2011Assignee: SanDisk 3D LLCInventors: Aldo Bottelli, Luca Fasoli
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Patent number: 7966532Abstract: Column redundancy data is selectively retrieved in a memory device according to a set of storage elements which is currently being accessed, such as in a read or write operation. The memory device is organized into sets of storage elements such as logical blocks, where column redundancy data is loaded from a non-volatile storage location to a volatile storage location for one or more particular blocks which are being accessed. The volatile storage location need only be large enough to store the current data entries. The size of the set of storage elements for which column redundancy data is concurrently loaded can be configured based on an expected maximum number of defects and a desired repair probability. During a manufacturing lifecycle, the size of the set can be increased as the number of defects is reduced due to improvements in manufacturing processes and materials.Type: GrantFiled: March 31, 2009Date of Patent: June 21, 2011Assignee: SanDisk 3D, LLCInventors: Aldo Bottelli, Luca Fasoli, Doug Sojourner
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Publication number: 20110002169Abstract: Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data, although this may be done at a penalty of under programming for some bits, as is described further below. A self contained Built In Self Test (BIST) flow constructed to collect the bit information through a set of column tests is also described.Type: ApplicationFiled: July 6, 2009Publication date: January 6, 2011Inventors: Yan Li, Kwang-ho Kim, Frank W. Tsai, Aldo Bottelli
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Publication number: 20100107022Abstract: A technique for identifying bad pages of storage elements in a memory device. A flag byte is provided for each page group of one or more pages which indicates whether the page group is healthy. Flag bytes of selected page groups also indicate whether larger sets of page groups are healthy, according to bit positions in the flag bytes. A bad page identification process includes reading the flag bytes with a selected granularity so that not all flag bytes are read. Optionally, a drill down process reads flag bytes for smaller sets of page groups when a larger set of page groups is identified as having at least one bad page. This allows the bad page groups to be identified and marked with greater specificity. Redundant copies of flag bytes may be stored in different locations of the memory device. A majority vote process assigns a value to each bit.Type: ApplicationFiled: March 9, 2009Publication date: April 29, 2010Inventors: Aldo Bottelli, Luca Fasoli
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Publication number: 20100107004Abstract: Column redundancy data is selectively retrieved in a memory device according to a set of storage elements which is currently being accessed, such as in a read or write operation. The memory device is organized into sets of storage elements such as logical blocks, where column redundancy data is loaded from a non-volatile storage location to a volatile storage location for one or more particular blocks which are being accessed. The volatile storage location need only be large enough to store the current data entries. The size of the set of storage elements for which column redundancy data is concurrently loaded can be configured based on an expected maximum number of defects and a desired repair probability. During a manufacturing lifecycle, the size of the set can be increased as the number of defects is reduced due to improvements in manufacturing processes and materials.Type: ApplicationFiled: March 31, 2009Publication date: April 29, 2010Inventors: Aldo Bottelli, Luca Fasoli, Doug Sojourner