Abstract: A device that provides for adaptive wear levelling includes at least one processor. The at least one processor utilizes sets of blocks of flash memory circuits for data storage operations, each set of blocks including a block from each flash memory circuit and at least some of the blocks being marked active for the data storage operations. The at least one processor monitors a quality metric of each block while the blocks marked active are utilized for data storage operations. The at least one processor determines when the quality metric of a block falls below a minimum level and marks the block as temporarily inactive, where the block is not utilized for the data storage operations while marked temporarily inactive. The at least one processor, when a criterion is satisfied, marks the block as active so that the block can again be utilized for the data storage operations.

Abstract: A device that provides for adaptive wear levelling includes at least one processor. The at least one processor utilizes sets of blocks of flash memory circuits for data storage operations, each set of blocks including a block from each flash memory circuit and at least some of the blocks being marked active for the data storage operations. The at least one processor monitors a quality metric of each block while the blocks marked active are utilized for data storage operations. The at least one processor determines when the quality metric of a block falls below a minimum level and marks the block as temporarily inactive, where the block is not utilized for the data storage operations while marked temporarily inactive. The at least one processor, when a criterion is satisfied, marks the block as active so that the block can again be utilized for the data storage operations.

Abstract: Reading requested data from flash memory using a first read level voltage. A number of first bit-value errors and a number of second bit-value errors is determined from the read requested data. An error ratio of the number of first bit-value errors and the number of second bit-value errors is compared to an error-ratio range. The first level voltage is adjusted based on the comparison of the error ratio to the error-ratio range.

Abstract: Reading requested data from flash memory using a first read level voltage. A number of first bit-value errors and a number of second bit-value errors is determined from the read requested data. An error ratio of the number of first bit-value errors and the number of second bit-value errors is compared to an error-ratio range. The first level voltage is adjusted based on the comparison of the error ratio to the error-ratio range.

Abstract: Disclosed is an apparatus and method for determining memory cell bias information for use in memory operations. One or more memory die are selected from a group of memory die, and one or more memory blocks selected from the selected one or more memory die. A group of cells within the selected memory blocks are programmed and cycled. Bias values are generated based on comparing one or more program levels associated with respective wordlines with predetermined programming levels. The bias values are stored lookup table that is configured to be accessible at runtime by a memory controller for retrieval of the bias value during a memory operation.

Abstract: Disclosed is an apparatus and method for determining memory cell bias information for use in memory operations. One or more memory die are selected from a group of memory die, and one or more memory blocks selected from the selected one or more memory die. A group of cells within the selected memory blocks are programmed and cycled. Bias values are generated based on comparing one or more program levels associated with respective wordlines with predetermined programming levels. The bias values are stored lookup table that is configured to be accessible at runtime by a memory controller for retrieval of the bias value during a memory operation.

Abstract: Systems and methods are disclosed for decoding solid-state memory cells using one-read soft decision decoding. A controller of a data storage device is configured to perform a first decoding of a first code word based at least in part on data associated with a reading of the first code word, and to detect a decoding failure associated with the first decoding. The controller determines reliability information for decoding the first code word in response to the decoding failure based at least in part on data associated with a successful decoding of a second code word and performs a second decoding of the first code word based at least in part on the reliability information.

Abstract: Disclosed is an apparatus and method for adjusting operating parameters in a storage device. A controller in a solid state drive monitors current operating conditions of the drive's flash memory, and when the flash memory has been subjected to a predetermined number of program/erase cycles one or more stored bias values are retrieved from a storage location based on the wordline(s) associated with a current memory operation. Parameters of the memory operation are then adjusted based on the retrieved bias values, and the memory operation is performed using the adjusted parameters.

Abstract: Disclosed is an apparatus and method for providing memory cell bias information for use in memory operations. One or more memory die are selected from a group of memory die, and one or more memory blocks selected from the selected one or more memory die. A group of cells are programmed within the selected memory blocks, and one or more distributions of cell program levels associated with a group of wordlines are determined. A bias value for each wordline is then generated based on comparing one or more program levels in a distribution of program levels associated with the respective wordline with predetermined programming levels. The bias values are stored lookup table that is configured to be accessible at runtime by a memory controller for retrieval of the bias value during a program or read operation.

Abstract: Disclosed is an apparatus and method for adjusting operating parameters in a storage device. A controller in a solid state drive monitors current operating conditions of the drive's flash memory, and when the flash memory has been subjected to a predetermined number of program/erase cycles one or more stored bias values are retrieved from a storage location based on the wordline(s) associated with a current memory operation. Parameters of the memory operation are then adjusted based on the retrieved bias values, and the memory operation is performed using the adjusted parameters.

Abstract: Systems and methods for programming data in a non-volatile memory array are disclosed. Certain embodiments provide a controller configured to program a lower page of a plurality of memory cells of the non-volatile memory array. The controller may submit the programmed lower page to an error correction module and receive correction data relating to the lower page from the error correction module. The correction data is used to program an upper page of the plurality of memory cells in order to at least partially reduce upper page misprogramming events.

Abstract: Disclosed is an apparatus and method for adjusting operating parameters in a storage device. A controller in a solid state drive monitors current operating conditions for blocks of memory used to store data in the drive. When a block has been subjected to a predetermined number of program/erase cycles one or more stored bias values are retrieved from a storage location based on the wordline(s) associated with a current memory operation. The one or more parameters of the memory operation are then adjusted based on the one or more stored bias values, and the memory operation performed on the block of memory cells using the adjusted parameters.

Abstract: Systems and methods are disclosed for decoding solid-state memory cells. In certain embodiments, a data storage device includes a controller configured to decode a non-volatile memory array by performing a first read of a plurality of code words from the non-volatile memory array using a first reference voltage level and performing a second read of the plurality of code words using a second reference voltage level on a first side of the first reference voltage level. The controller is further configured to generate a soft-decision input value associated with a first code word of the plurality of code words based on the first and second reads and decode the first code word using the soft-decision input value.

Abstract: Disclosed is an apparatus and method for determining a read level voltage to apply to a block of memory cells in a non-volatile memory circuit. A prediction value is compared to a prediction indicator to determine whether a new read level voltage to be applied to read the memory cells should be estimated. If a new read level should be estimated the new read level is calculated as a function of an initial read level and a dwell time and a number of program/erase cycles. A controller provides one or more programming commands representative of the new read level voltage to the memory circuit to read the cells.

Abstract: Disclosed is an apparatus and method for determining a dwell time in a non-volatile memory circuit after a shutdown of the memory circuit. A voltage shift is calculated by comparing a first read level voltage required to read a test block stored before the shutdown and a second read level voltage required to read a second test block stored after the shutdown. A shutdown time is determined from a look up table indexed by the voltage shift and a number of program/erase cycles. The dwell time is calculated as a function of the drive temperature, a clock, and a block time stamp. Once the dwell time is calculated, a controller calculates a new read level voltage based, in part, on the dwell time and provides one or more programming commands representative of the new read level voltage to the memory circuit to read the memory circuit.

Abstract: Disclosed is an apparatus and method for determining a dwell time in a non-volatile memory circuit after a shutdown of the memory circuit. A voltage shift is calculated by comparing a first read level voltage required to read a test block stored before the shutdown and a second read level voltage required to read a second test block stored after the shutdown. A shutdown time is determined from a look up table indexed by the voltage shift and a number of program/erase cycles. The dwell time is calculated as a function of the drive temperature, a clock, and a block time stamp. Once the dwell time is calculated, a controller calculates a new read level voltage based, in part, on the dwell time and provides one or more programming commands representative of the new read level voltage to the memory circuit to read the memory circuit.

Abstract: Disclosed is an apparatus and method for determining a read level voltage to apply to a block of memory cells in a non-volatile memory circuit. A prediction value is compared to a prediction indicator to determine whether a new read level voltage to be applied to read the memory cells should be estimated. If a new read level should be estimated the new read level is calculated as a function of an initial read level and a dwell time and a number of program/erase cycles. A controller provides one or more programming commands representative of the new read level voltage to the memory circuit to read the cells.