Patents by Inventor Aldo Giovanni Cometti

Aldo Giovanni Cometti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11190218
    Abstract: A data storage system capable of switching a code rate based on a host command is disclosed. A controller of the data storage system may set a code rate in a data storage device to a first code rate for encoding data to be written to non-volatile memory of the data storage device. The controller may receive, at the data storage device, a host command indicating a switch point for switching the set code rate from the first code rate to a second code rate. The controller may switch the set code rate from the first code rate to the second code rate at the indicated switch point.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: November 30, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Aldo Giovanni Cometti, Aniryudh Reddy Durgam
  • Publication number: 20210319837
    Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.
    Type: Application
    Filed: June 25, 2021
    Publication date: October 14, 2021
    Inventors: Richard David BARNDT, Aldo Giovanni COMETTI, Richard Leo GALBRAITH, Jonas Andrew GOODE, Niranjay RAVINDRAN, Anthony Dwayne WEATHERS
  • Patent number: 11101006
    Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: August 24, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Richard David Barndt, Aldo Giovanni Cometti, Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran, Anthony Dwayne Weathers
  • Publication number: 20200335173
    Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Inventors: Richard David BARNDT, Aldo Giovanni COMETTI, Richard Leo GALBRAITH, Jonas Andrew GOODE, Niranjay RAVINDRAN, Anthony Dwayne WEATHERS
  • Patent number: 10748628
    Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: August 18, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Richard David Barndt, Aldo Giovanni Cometti, Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran, Anthony Dwayne Weathers
  • Publication number: 20200220561
    Abstract: A data storage system capable of switching a code rate based on a host command is disclosed. A controller of the data storage system may set a code rate in a data storage device to a first code rate for encoding data to be written to non-volatile memory of the data storage device. The controller may receive, at the data storage device, a host command indicating a switch point for switching the set code rate from the first code rate to a second code rate. The controller may switch the set code rate from the first code rate to the second code rate at the indicated switch point.
    Type: Application
    Filed: March 20, 2020
    Publication date: July 9, 2020
    Inventors: Aldo Giovanni COMETTI, Aniryudh Reddy DURGAM
  • Patent number: 10644727
    Abstract: A data storage system capable of switching a code rate based on a host command is disclosed. A controller of the data storage system may set a code rate in a data storage device to a first code rate for encoding data to be written to non-volatile memory of the data storage device. The controller may receive, at the data storage device, a host command indicating a switch point for switching the set code rate from the first code rate to a second code rate. The controller may switch the set code rate from the first code rate to the second code rate at the indicated switch point.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: May 5, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Aldo Giovanni Cometti, Aniryudh Reddy Durgam
  • Patent number: 10545810
    Abstract: Aspects of the disclosure provide a method and an apparatus that perform a background media scan (BGMS) with improved efficiency. In particular, the disclosed BGMS processes can monitor data retention performance of a large capacity solid state drive (SSD) without significantly increasing scanning overhead by scanning only some sample pages of a memory block.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: January 28, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Richard David Barndt, Hung-min Chang, Aldo Giovanni Cometti, Jerry Lo, Hung-Cheng Yeh
  • Patent number: 10496334
    Abstract: Aspects of the present disclosure provide systems and methods for operating a solid state drive (SSD) using two-level indirection architecture. The SSD receives a command to perform a data operation in a NAND array and a logical address for the data operation. The SSD then converts the logical address to a physical address using a two-stage logical-to-physical (L2P) mapping table that includes a first stage stored in a byte-rewritable memory and a second stage stored in a block-erasable non-volatile memory (NVM). The SSD performs the data operation in the NAND array based on the physical address. The byte-rewritable memory may any byte-rewritable persistent memory. The block-erasable low latency NVM may be a flash memory that has lower latency than NAND array.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: December 3, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Mark David Myran, Chandan Mishra, Amir Hossein Gholamipour, Aldo Giovanni Cometti, Namhoon Yoo
  • Publication number: 20190339904
    Abstract: Aspects of the present disclosure provide systems and methods for operating a solid state drive (SSD) using two-level indirection architecture. The SSD receives a command to perform a data operation in a NAND array and a logical address for the data operation. The SSD then converts the logical address to a physical address using a two-stage logical-to-physical (L2P) mapping table that includes a first stage stored in a byte-rewritable memory and a second stage stored in a block-erasable non-volatile memory (NVM). The SSD performs the data operation in the NAND array based on the physical address. The byte-rewritable memory may any byte-rewritable persistent memory. The block-erasable low latency NVM may be a flash memory that has lower latency than NAND array.
    Type: Application
    Filed: May 4, 2018
    Publication date: November 7, 2019
    Inventors: Mark David Myran, Chandan Mishra, Amir Hossein Gholamipour, Aldo Giovanni Cometti, Namhoon Yoo
  • Patent number: 10373695
    Abstract: Aspects of the disclosure provide methods and apparatus for handling Read Disturb and block errors in a non-volatile memory (NVM) device. An error level of both an aggressor page that causes Read Disturb errors and an error level of adjacent victim pages are obtained. The error level of the victim page is compared against a predetermined threshold error level to determine if the victim page is experiencing a high level of bit errors. If so, then the error level of the aggressor page is compared to the error level of the victim page to determine whether Read Disturb errors are actually occurring due to host reads of the aggressor page. By looking at both the aggressor and victim error levels, a more accurate determination of Read Disturb errors may be obtained, resulting in less unnecessary relocations of pages and blocks within an NVM for mitigating Read Disturb effects.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: August 6, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Richard David Barndt, Aldo Giovanni Cometti, Haining Liu, Jerry Lo
  • Publication number: 20190214101
    Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.
    Type: Application
    Filed: March 14, 2019
    Publication date: July 11, 2019
    Inventors: Richard David Barndt, Aldo Giovanni Cometti, Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran, Anthony Dwayne Weathers
  • Publication number: 20190215016
    Abstract: A data storage system capable of switching a code rate based on a host command is disclosed. A controller of the data storage system may set a code rate in a data storage device to a first code rate for encoding data to be written to non-volatile memory of the data storage device. The controller may receive, at the data storage device, a host command indicating a switch point for switching the set code rate from the first code rate to a second code rate. The controller may switch the set code rate from the first code rate to the second code rate at the indicated switch point.
    Type: Application
    Filed: January 11, 2018
    Publication date: July 11, 2019
    Inventors: Aldo Giovanni COMETTI, Aniryudh Reddy DURGAM
  • Patent number: 10236070
    Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: March 19, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Richard David Barndt, Aldo Giovanni Cometti, Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran, Anthony Dwayne Weathers
  • Publication number: 20180374550
    Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.
    Type: Application
    Filed: July 31, 2017
    Publication date: December 27, 2018
    Inventors: Richard David BARNDT, Aldo Giovanni COMETTI, Richard Leo GALBRAITH, Jonas Andrew GOODE, Niranjay RAVINDRAN, Anthony Dwayne WEATHERS
  • Publication number: 20180190362
    Abstract: Aspects of the disclosure provide methods and apparatus for handling Read Disturb and block errors in a non-volatile memory (NVM) device. An error level of both an aggressor page that causes Read Disturb errors and an error level of adjacent victim pages are obtained. The error level of the victim page is compared against a predetermined threshold error level to determine if the victim page is experiencing a high level of bit errors. If so, then the error level of the aggressor page is compared to the error level of the victim page to determine whether Read Disturb errors are actually occurring due to host reads of the aggressor page. By looking at both the aggressor and victim error levels, a more accurate determination of Read Disturb errors may be obtained, resulting in less unnecessary relocations of pages and blocks within an NVM for mitigating Read Disturb effects.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventors: Richard David Barndt, Aldo Giovanni Cometti, Haining Liu, Jerry Lo
  • Publication number: 20180181300
    Abstract: Aspects of the disclosure provide a method and an apparatus that perform a background media scan (BGMS) with improved efficiency. In particular, the disclosed BGMS processes can monitor data retention performance of a large capacity solid state drive (SSD) without significantly increasing scanning overhead by scanning only some sample pages of a memory block.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 28, 2018
    Inventors: Richard David Barndt, Hung-min Chang, Aldo Giovanni Cometti, Jerry Lo, Hung-Cheng Yeh
  • Patent number: 5777498
    Abstract: A circuit that compensates for delays induced by clock generation logic and distributed clock drivers in phase lock loop applications is disclosed. The circuit is a phase lock loop (PLL) which contains a clock synchronization circuit that operates to synchronize a transition edge of a signal generated by a frequency divider against a distributed clock signal generated by a clock output driver of the circuit. The synchronization occurs unless the clock synchronization circuit is disabled.
    Type: Grant
    Filed: December 2, 1996
    Date of Patent: July 7, 1998
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: Aldo Giovanni Cometti, R. Frank O'Bleness
  • Patent number: RE38045
    Abstract: A circuit that compensates for delays induced by clock generation logic and distributed clock drivers in phase lock loop applications is disclosed. The circuit is a phase lock loop (PLL) which contains a clock synchronization circuit that operates to synchronize a transition edge of a signal generated by a frequency divider against a distributed clock signal generated by a clock output driver of the circuit. The synchronization occurs unless the clock synchronization circuit is disabled.
    Type: Grant
    Filed: July 7, 2000
    Date of Patent: March 25, 2003
    Assignee: STMicroelectronics, Inc.
    Inventors: Aldo Giovanni Cometti, R. Frank O'Bleness