Patents by Inventor Aldo Giovanni Cometti
Aldo Giovanni Cometti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11621043Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.Type: GrantFiled: June 25, 2021Date of Patent: April 4, 2023Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Richard David Barndt, Aldo Giovanni Cometti, Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran, Anthony Dwayne Weathers
-
Patent number: 11190218Abstract: A data storage system capable of switching a code rate based on a host command is disclosed. A controller of the data storage system may set a code rate in a data storage device to a first code rate for encoding data to be written to non-volatile memory of the data storage device. The controller may receive, at the data storage device, a host command indicating a switch point for switching the set code rate from the first code rate to a second code rate. The controller may switch the set code rate from the first code rate to the second code rate at the indicated switch point.Type: GrantFiled: March 20, 2020Date of Patent: November 30, 2021Assignee: Western Digital Technologies, Inc.Inventors: Aldo Giovanni Cometti, Aniryudh Reddy Durgam
-
Publication number: 20210319837Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.Type: ApplicationFiled: June 25, 2021Publication date: October 14, 2021Inventors: Richard David BARNDT, Aldo Giovanni COMETTI, Richard Leo GALBRAITH, Jonas Andrew GOODE, Niranjay RAVINDRAN, Anthony Dwayne WEATHERS
-
Patent number: 11101006Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.Type: GrantFiled: July 6, 2020Date of Patent: August 24, 2021Assignee: Western Digital Technologies, Inc.Inventors: Richard David Barndt, Aldo Giovanni Cometti, Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran, Anthony Dwayne Weathers
-
Publication number: 20200335173Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.Type: ApplicationFiled: July 6, 2020Publication date: October 22, 2020Inventors: Richard David BARNDT, Aldo Giovanni COMETTI, Richard Leo GALBRAITH, Jonas Andrew GOODE, Niranjay RAVINDRAN, Anthony Dwayne WEATHERS
-
Patent number: 10748628Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.Type: GrantFiled: March 14, 2019Date of Patent: August 18, 2020Assignee: Western Digital Technologies, Inc.Inventors: Richard David Barndt, Aldo Giovanni Cometti, Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran, Anthony Dwayne Weathers
-
Publication number: 20200220561Abstract: A data storage system capable of switching a code rate based on a host command is disclosed. A controller of the data storage system may set a code rate in a data storage device to a first code rate for encoding data to be written to non-volatile memory of the data storage device. The controller may receive, at the data storage device, a host command indicating a switch point for switching the set code rate from the first code rate to a second code rate. The controller may switch the set code rate from the first code rate to the second code rate at the indicated switch point.Type: ApplicationFiled: March 20, 2020Publication date: July 9, 2020Inventors: Aldo Giovanni COMETTI, Aniryudh Reddy DURGAM
-
Patent number: 10644727Abstract: A data storage system capable of switching a code rate based on a host command is disclosed. A controller of the data storage system may set a code rate in a data storage device to a first code rate for encoding data to be written to non-volatile memory of the data storage device. The controller may receive, at the data storage device, a host command indicating a switch point for switching the set code rate from the first code rate to a second code rate. The controller may switch the set code rate from the first code rate to the second code rate at the indicated switch point.Type: GrantFiled: January 11, 2018Date of Patent: May 5, 2020Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Aldo Giovanni Cometti, Aniryudh Reddy Durgam
-
Patent number: 10545810Abstract: Aspects of the disclosure provide a method and an apparatus that perform a background media scan (BGMS) with improved efficiency. In particular, the disclosed BGMS processes can monitor data retention performance of a large capacity solid state drive (SSD) without significantly increasing scanning overhead by scanning only some sample pages of a memory block.Type: GrantFiled: December 22, 2016Date of Patent: January 28, 2020Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Richard David Barndt, Hung-min Chang, Aldo Giovanni Cometti, Jerry Lo, Hung-Cheng Yeh
-
Patent number: 10496334Abstract: Aspects of the present disclosure provide systems and methods for operating a solid state drive (SSD) using two-level indirection architecture. The SSD receives a command to perform a data operation in a NAND array and a logical address for the data operation. The SSD then converts the logical address to a physical address using a two-stage logical-to-physical (L2P) mapping table that includes a first stage stored in a byte-rewritable memory and a second stage stored in a block-erasable non-volatile memory (NVM). The SSD performs the data operation in the NAND array based on the physical address. The byte-rewritable memory may any byte-rewritable persistent memory. The block-erasable low latency NVM may be a flash memory that has lower latency than NAND array.Type: GrantFiled: May 4, 2018Date of Patent: December 3, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Mark David Myran, Chandan Mishra, Amir Hossein Gholamipour, Aldo Giovanni Cometti, Namhoon Yoo
-
Publication number: 20190339904Abstract: Aspects of the present disclosure provide systems and methods for operating a solid state drive (SSD) using two-level indirection architecture. The SSD receives a command to perform a data operation in a NAND array and a logical address for the data operation. The SSD then converts the logical address to a physical address using a two-stage logical-to-physical (L2P) mapping table that includes a first stage stored in a byte-rewritable memory and a second stage stored in a block-erasable non-volatile memory (NVM). The SSD performs the data operation in the NAND array based on the physical address. The byte-rewritable memory may any byte-rewritable persistent memory. The block-erasable low latency NVM may be a flash memory that has lower latency than NAND array.Type: ApplicationFiled: May 4, 2018Publication date: November 7, 2019Inventors: Mark David Myran, Chandan Mishra, Amir Hossein Gholamipour, Aldo Giovanni Cometti, Namhoon Yoo
-
Patent number: 10373695Abstract: Aspects of the disclosure provide methods and apparatus for handling Read Disturb and block errors in a non-volatile memory (NVM) device. An error level of both an aggressor page that causes Read Disturb errors and an error level of adjacent victim pages are obtained. The error level of the victim page is compared against a predetermined threshold error level to determine if the victim page is experiencing a high level of bit errors. If so, then the error level of the aggressor page is compared to the error level of the victim page to determine whether Read Disturb errors are actually occurring due to host reads of the aggressor page. By looking at both the aggressor and victim error levels, a more accurate determination of Read Disturb errors may be obtained, resulting in less unnecessary relocations of pages and blocks within an NVM for mitigating Read Disturb effects.Type: GrantFiled: December 30, 2016Date of Patent: August 6, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Richard David Barndt, Aldo Giovanni Cometti, Haining Liu, Jerry Lo
-
Publication number: 20190214101Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.Type: ApplicationFiled: March 14, 2019Publication date: July 11, 2019Inventors: Richard David Barndt, Aldo Giovanni Cometti, Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran, Anthony Dwayne Weathers
-
Publication number: 20190215016Abstract: A data storage system capable of switching a code rate based on a host command is disclosed. A controller of the data storage system may set a code rate in a data storage device to a first code rate for encoding data to be written to non-volatile memory of the data storage device. The controller may receive, at the data storage device, a host command indicating a switch point for switching the set code rate from the first code rate to a second code rate. The controller may switch the set code rate from the first code rate to the second code rate at the indicated switch point.Type: ApplicationFiled: January 11, 2018Publication date: July 11, 2019Inventors: Aldo Giovanni COMETTI, Aniryudh Reddy DURGAM
-
Patent number: 10236070Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.Type: GrantFiled: July 31, 2017Date of Patent: March 19, 2019Assignee: Western Digital Technologies, Inc.Inventors: Richard David Barndt, Aldo Giovanni Cometti, Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran, Anthony Dwayne Weathers
-
Publication number: 20180374550Abstract: Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.Type: ApplicationFiled: July 31, 2017Publication date: December 27, 2018Inventors: Richard David BARNDT, Aldo Giovanni COMETTI, Richard Leo GALBRAITH, Jonas Andrew GOODE, Niranjay RAVINDRAN, Anthony Dwayne WEATHERS
-
Publication number: 20180190362Abstract: Aspects of the disclosure provide methods and apparatus for handling Read Disturb and block errors in a non-volatile memory (NVM) device. An error level of both an aggressor page that causes Read Disturb errors and an error level of adjacent victim pages are obtained. The error level of the victim page is compared against a predetermined threshold error level to determine if the victim page is experiencing a high level of bit errors. If so, then the error level of the aggressor page is compared to the error level of the victim page to determine whether Read Disturb errors are actually occurring due to host reads of the aggressor page. By looking at both the aggressor and victim error levels, a more accurate determination of Read Disturb errors may be obtained, resulting in less unnecessary relocations of pages and blocks within an NVM for mitigating Read Disturb effects.Type: ApplicationFiled: December 30, 2016Publication date: July 5, 2018Inventors: Richard David Barndt, Aldo Giovanni Cometti, Haining Liu, Jerry Lo
-
Publication number: 20180181300Abstract: Aspects of the disclosure provide a method and an apparatus that perform a background media scan (BGMS) with improved efficiency. In particular, the disclosed BGMS processes can monitor data retention performance of a large capacity solid state drive (SSD) without significantly increasing scanning overhead by scanning only some sample pages of a memory block.Type: ApplicationFiled: December 22, 2016Publication date: June 28, 2018Inventors: Richard David Barndt, Hung-min Chang, Aldo Giovanni Cometti, Jerry Lo, Hung-Cheng Yeh
-
Patent number: 5777498Abstract: A circuit that compensates for delays induced by clock generation logic and distributed clock drivers in phase lock loop applications is disclosed. The circuit is a phase lock loop (PLL) which contains a clock synchronization circuit that operates to synchronize a transition edge of a signal generated by a frequency divider against a distributed clock signal generated by a clock output driver of the circuit. The synchronization occurs unless the clock synchronization circuit is disabled.Type: GrantFiled: December 2, 1996Date of Patent: July 7, 1998Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Aldo Giovanni Cometti, R. Frank O'Bleness
-
Patent number: RE38045Abstract: A circuit that compensates for delays induced by clock generation logic and distributed clock drivers in phase lock loop applications is disclosed. The circuit is a phase lock loop (PLL) which contains a clock synchronization circuit that operates to synchronize a transition edge of a signal generated by a frequency divider against a distributed clock signal generated by a clock output driver of the circuit. The synchronization occurs unless the clock synchronization circuit is disabled.Type: GrantFiled: July 7, 2000Date of Patent: March 25, 2003Assignee: STMicroelectronics, Inc.Inventors: Aldo Giovanni Cometti, R. Frank O'Bleness