Abstract: A train of signals is generated by clocking an 8-bit word from an 8-bit shift register which has been loaded with an initial data word. The register is provided with feedback loop. The serial data is supplied along a communication link to a similar or identical 8-bit shift register at the receiving end of the link. A comparator compares the output data of the register with the first stage of the register and provides an accept signal provided such comparison indicates inversions at the receipt of each bit for 9-bits onwards. After transmission of 24-bits, the shift register contains the 8-bit data word, which has been checked twice for any inaccuracy.