Patents by Inventor Alec S. Adair

Alec S. Adair has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED CIRCUIT DESIGN, CONTEXTUAL CELLS, DESIGN MIGRATION, AND ASSOCIATED METHODS
    Publication number: 20240028809
    Abstract: Methods are disclosed. A method may include a method of generating an integrated circuit design. The method of generating an integrated circuit design may include generating a contextual cell including a super-master and defining at least one sub-master, the at least one sub-master derived from parameterized values and a context of an instance of the super-master.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 25, 2024
    Inventors: Thomas L. Wolf, Kent F. Smith, Tracy L. Johancsik, Alec S. Adair, Kyler C. Fillerup, Stuart T. Anderson, Thomas G. Wolf
  • PARAMETERIZED HIGH LEVEL HIERARCHICAL MODELING, AND ASSOCIATED METHODS
    Publication number: 20240028803
    Abstract: A method may include obtaining a netlist representation of a circuit comprising a single-cell (S-Cell) or multi-cell (M-Cell), performing one or more test simulations using the netlist representation of the circuit, receiving one or more parameters comprising performance metrics of the circuit responsive to the one or more test simulations, and generating a parameterized model of the circuit responsive to the one or more parameters.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 25, 2024
    Inventors: Thomas L. Wolf, Alec S. Adair, Stuart T. Anderson, Kyler C. Fillerup, Tracy L. Johancsik, Jared Bytheway