Abstract: A word line decode circuit may include three devices, a first p-type transistor, a first n-type transistor and a second n-type transistor together with a shared (with other word line decoding circuits) p-type transistor make up a “distributed” NOR gate. The first p-type transistor and the first n-type transistor may be toggled via the lowest level decode signal. To select a wordline, this low level decode signal may be low as well as a signal provided to the gate of the shared p-type transistor. The signal to the gate of the shared p-type transistor may be an output of a ratioed logic level shifter.

Abstract: According to some embodiments, a memory device having multiple memory units includes one or more redundant memory units. Upon detection of an electrical characteristic indicating a failing memory unit, one of the redundant memory units is used to replace the failing memory unit. Detection of failing memory units may be via current, voltage and/or resistance monitoring. If the electrical characteristic monitored exceeds a predetermined threshold, a memory unit is considered failing. The failing memory unit is removed from further use. The redundant memory unit is programmed to be accessible at the memory address of the removed memory unit. Replacement occurs automatically (that is, without user intervention).