Abstract: A method for improving a nominal output of a thin-film solar module with a laminated composite of two substrates which are connected to each other by at least one adhesive layer and between which there are solar cells connected in series is described. The method relates to solar cells being illuminated with an artificial light with an irradiance of at least 5 kW/m2.

Abstract: A solar module is described. The solar module has a laminated composite of two substrates bonded to one another by at least one bonding layer, between which substrates there are solar cells which are connected in series and which each have an absorber zone made of a semiconducting material between a front electrode arranged on a light entrance side of the absorber zone and a rear electrode. A diffusion barrier differing from the front electrode is located between each absorber zone and the bonding layer and is designed to inhibit the diffusion of water molecules from the bonding layer into the absorber zone and/or the diffusion of dopant ions from the absorber zone into the bonding layer. A process for producing such a solar module is also described.

Abstract: A method for improving a nominal output of a thin-film solar module with a laminated composite of two substrates which are connected to each other by at least one adhesive layer and between which there are solar cells connected in series is described. The method relates to solar cells being illuminated with an artificial light with an irradiance of at least 5 kW/m2.

Abstract: One embodiment relates to an integrated circuit that includes a conductive line that is arranged in a groove in a semiconductor body. An insulating material is disposed over the conductive line. This insulating material includes a first insulating layer comprising a horizontal portion, and a second insulating layer that is disposed over the first insulating layer. Other methods, devices, and systems are also disclosed.

Abstract: An electrical component, such as a DRAM semiconductor memory or a field-effect transistor is fabricated. At least one capacitor having a dielectric (130) and at least one connection electrode (120, 140) are fabricated. To enable the capacitors fabricated to have optimum storage properties even for very small capacitor structures, the dielectric (130) or the connection electrode (120, 140) are formed in such a manner that transient polarization effects are prevented or at least reduced.

Abstract: An integrated circuit including a dielectric layer and a method for producing an integrated circuit. In one embodiment, a dielectric layer is deposited in a process atmosphere. The process atmosphere includes a first starting component at a first point in time, a second starting component at a second point in time and a third starting component at a third point in time. The third starting component includes a halogen.

Abstract: The invention refers to a selective deposition method. A substrate comprising at least one structured surface is provided. The structured surface comprises a first area and a second area. The first area is selectively passivated regarding reactants of a first deposition technique and the second area is activated regarding the reactants the first deposition technique. A passivation layer on the second area is deposited via the first deposition technique. The passivation layer is inert regarding a precursors selected from a group of oxidizing reactants. A layer is deposited in the second area using a second atomic layer deposition technique as second deposition technique using the precursors selected form the group of oxidizing reactants.

Abstract: A semiconductor product includes an exposed Hafnium-containing layer. The Hafnium-containing layer is treated with a solution that includes a low ionic strength organic substance.

Abstract: It is one object to devise a solution which is suitable for a wet treatment of Hafnium containing high-k materials. Furthermore, it is an object to devise a use of this solution in the field of semiconductor device manufacturing. It is also an objective of the invention to devise a process to this aim.

Abstract: Memory and method for fabricating it A memory formed as an integrated circuit in a semiconductor substrate and having storage capacitors and switching transistors. The storage capacitors are formed in the semiconductor substrate in a trench and have an outer electrode layer, which is formed around the trench, a dielectric intermediate layer, which is embodied on the trench wall, and an inner electrode layer, with which the trench is essentially filled, and the switching transistors are formed in the semiconductor substrate in a surface region and have a first source/drain doping region, a second source/drain doping region and an intervening channel, which is separated from a gate electrode by an insulator layer.

Abstract: An electrical component, such as a DRAM semiconductor memory or a field-effect transistor is fabricated. At least one capacitor having a dielectric (130) and at least one connection electrode (120, 140) are fabricated. To enable the capacitors fabricated to have optimum storage properties even for very small capacitor structures, the dielectric (130) or the connection electrode (120, 140) are formed in such a manner that transient polarization effects are prevented or at least reduced.

Abstract: A storage capacitor, suitable for use in a DRAM cell, is at least partially formed above a substrate surface and includes: a storage electrode at least partially formed above the substrate surface, a dielectric layer formed adjacent the storage electrode, and a counter electrode formed adjacent the dielectric layer, the counter electrode being isolated from the storage electrode by the dielectric layer, wherein the storage electrode is formed as a body which is delimited by at least one curved surface having a center of curvature outside the body in a plane parallel to the substrate surface. According to another configuration, the storage electrode is formed as a body which is delimited by at least one set having two contiguous planes, the two planes extending perpendicularly with respect to the substrate surface, a point of intersection of normals of the two planes lying outside the body.