Patents by Inventor Alejandro F. Gonzalez
Alejandro F. Gonzalez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10956349Abstract: An apparatus includes a control circuit comprising (i) a first differential data strobe input/output circuit having a first set of driver and termination control inputs and (ii) a second differential data strobe input/output circuit having a second set of driver and termination control inputs. The first and the second sets of driver and termination control inputs are independently programmable. The first and the second differential data strobe input/output circuits operate in a first mode when the first differential data strobe input/output circuit is connected to a first memory device having a first data width and the second differential data strobe input/output circuit is connected to a second memory device having the first data width.Type: GrantFiled: December 16, 2019Date of Patent: March 23, 2021Assignee: Integrated Device Technology, Inc.Inventors: Alejandro F. Gonzalez, Craig DeSimone, Garret Davey, Yue Yu, Roland Knaack, Scott Herrington
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Patent number: 10776293Abstract: An apparatus including a host interface and a registered clock driver interface. The host interface may be configured to receive an enable command from a host. The registered clock driver interface may be configured to perform power management for a dual in-line memory module, generate data for the dual in-line memory module, communicate the data, receive a clock signal and communicate an interrupt signal. The registered clock driver interface may be disabled at power on. The registered clock driver interface may be enabled by in response to the enable command. The apparatus may be implemented as a component on the dual in-line memory module.Type: GrantFiled: May 1, 2018Date of Patent: September 15, 2020Assignee: Integrated Device Technology, Inc.Inventors: Shwetal Arvind Patel, Andy Zhang, Wen Jie Meng, Chenxiao Ren, Alejandro F. Gonzalez
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Patent number: 10769082Abstract: An apparatus including a host interface and a power management interface. The host interface may be configured to receive control words from a host. The power management interface may be configured to (i) enable the host to read/write data from/to a power management circuit of a dual in-line memory module, (ii) communicate the data, (iii) generate a clock signal and (iv) communicate an interrupt signal. The power management interface is disabled at power on. The apparatus is configured to (i) decode the control words, (ii) enable the power management interface when the control words provide an enable command and (iii) perform a response to the interrupt signal. The clock signal may operate independently from a host clock.Type: GrantFiled: May 1, 2018Date of Patent: September 8, 2020Assignee: Integrated Device Technology, Inc.Inventors: Shwetal Arvind Patel, Andy Zhang, Wen Jie Meng, Chenxiao Ren, Alejandro F. Gonzalez
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Publication number: 20200117629Abstract: An apparatus includes a control circuit comprising (i) a first differential data strobe input/output circuit having a first set of driver and termination control inputs and (ii) a second differential data strobe input/output circuit having a second set of driver and termination control inputs. The first and the second sets of driver and termination control inputs are independently programmable. The first and the second differential data strobe input/output circuits operate in a first mode when the first differential data strobe input/output circuit is connected to a first memory device having a first data width and the second differential data strobe input/output circuit is connected to a second memory device having the first data width.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Alejandro F. Gonzalez, Craig DeSimone, Garret Davey, Yue Yu, Roland Knaack, Scott Herrington
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Patent number: 10565144Abstract: An apparatus includes a plurality of memory devices and a control circuit. The control circuit may be configured to operate with the memory devices having a first data width in a first mode and with the memory devices having a second data width in a second mode. The control circuit may be configured to implement two differential data strobe input/output circuits. The differential data strobe input/output circuits each may have driver and termination control inputs that are independently programmable. The differential data strobe input/output circuits may be configured to be connected in parallel when the control circuit is operating in the second mode.Type: GrantFiled: August 9, 2018Date of Patent: February 18, 2020Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.Inventors: Alejandro F. Gonzalez, Craig DeSimone, Garret Davey, Yue Yu, Roland Knaack, Scott Herrington
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Publication number: 20190340141Abstract: An apparatus including a host interface and a registered clock driver interface. The host interface may be configured to receive an enable command from a host. The registered clock driver interface may be configured to perform power management for a dual in-line memory module, generate data for the dual in-line memory module, communicate the data, receive a clock signal and communicate an interrupt signal. The registered clock driver interface may be disabled at power on. The registered clock driver interface may be enabled by in response to the enable command. The apparatus may be implemented as a component on the dual in-line memory module.Type: ApplicationFiled: May 1, 2018Publication date: November 7, 2019Inventors: Shwetal Arvind Patel, Andy Zhang, Wen Jie Meng, Chenxiao Ren, Alejandro F. Gonzalez
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Publication number: 20190340142Abstract: An apparatus including a host interface and a power management interface. The host interface may be configured to receive control words from a host. The power management interface may be configured to (i) enable the host to read/write data from/to a power management circuit of a dual in-line memory module, (ii) communicate the data, (iii) generate a clock signal and (iv) communicate an interrupt signal. The power management interface is disabled at power on. The apparatus is configured to (i) decode the control words, (ii) enable the power management interface when the control words provide an enable command and (iii) perform a response to the interrupt signal. The clock signal may operate independently from a host clock.Type: ApplicationFiled: May 1, 2018Publication date: November 7, 2019Inventors: Shwetal Arvind Patel, Andy Zhang, Wen Jie Meng, Chenxiao Ren, Alejandro F. Gonzalez
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Patent number: 10325637Abstract: An apparatus includes a plurality of memory devices and a control circuit. The control circuit may be configured to enable a plurality of access modes for the plurality of memory devices. In a one-channel mode, all of the memory devices are accessed using a single selectable channel. In a two-channel mode, a first portion of the plurality of memory devices is accessed using a first channel and a second portion of the plurality of memory devices is accessed using a second channel.Type: GrantFiled: July 24, 2018Date of Patent: June 18, 2019Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.Inventor: Alejandro F. Gonzalez
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Publication number: 20190129879Abstract: An apparatus includes a plurality of memory devices and a control circuit. The control circuit may be configured to operate with the memory devices having a first data width in a first mode and with the memory devices having a second data width in a second mode. The control circuit may be configured to implement two differential data strobe input/output circuits. The differential data strobe input/output circuits each may have driver and termination control inputs that are independently programmable. The differential data strobe input/output circuits may be configured to be connected in parallel when the control circuit is operating in the second mode.Type: ApplicationFiled: August 9, 2018Publication date: May 2, 2019Inventors: Alejandro F. Gonzalez, Craig DeSimone, Garret Davey, Yue Yu, Roland Knaack, Scott Herrington
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Publication number: 20190013054Abstract: An apparatus includes a plurality of memory devices and a control circuit. The control circuit may be configured to enable a plurality of access modes for the plurality of memory devices. In a one-channel mode, all of the memory devices are accessed using a single selectable channel. In a two-channel mode, a first portion of the plurality of memory devices is accessed using a first channel and a second portion of the plurality of memory devices is accessed using a second channel.Type: ApplicationFiled: July 24, 2018Publication date: January 10, 2019Inventor: Alejandro F. Gonzalez
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Patent number: 10032497Abstract: An apparatus includes a plurality of memory devices and a control circuit. The control circuit may be configured to enable a plurality of access modes for the plurality of memory devices. In a one-channel mode, all of the memory devices are accessed using a single selectable channel. In a two-channel mode, a first portion of the plurality of memory devices is accessed using a first channel and a second portion of the plurality of memory devices is accessed using a second channel.Type: GrantFiled: April 5, 2016Date of Patent: July 24, 2018Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.Inventor: Alejandro F. Gonzalez
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Publication number: 20170287538Abstract: An apparatus includes a plurality of memory devices and a control circuit. The control circuit may be configured to enable a plurality of access modes for the plurality of memory devices. In a one-channel mode, all of the memory devices are accessed using a single selectable channel. In a two-channel mode, a first portion of the plurality of memory devices is accessed using a first channel and a second portion of the plurality of memory devices is accessed using a second channel.Type: ApplicationFiled: April 5, 2016Publication date: October 5, 2017Inventor: Alejandro F. Gonzalez
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Patent number: 8693557Abstract: A clock receiver includes a capacitive coupling circuit for filtering out direct-current voltages from a differential clock signal. In this way, the capacitive coupling circuit rejects common-mode noise in the differential clock signal. The clock receiver also includes a bias circuit for establishing a bias voltage in the differential clock signal and a differential amplifier for amplifying the differential clock signal. Further, the differential amplifier generate a feedback differential clock signal and provides the feedback differential clock signal to the bias circuit for further rejecting common-mode noise in the differential clock signal. The feedback differential clock signal functions as a negative feedback signal for rejecting common-mode noise in the differential clock signal and as a positive feedback signal for amplifying the differential clock signal.Type: GrantFiled: July 2, 2009Date of Patent: April 8, 2014Assignee: Integrated Device Technology inc.Inventors: Liang Leon Zhang, Alejandro F. Gonzalez