Patents by Inventor Alejandro Hernandez-Luna

Alejandro Hernandez-Luna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11756882
    Abstract: A semiconductor package includes a metallic pad and leads, a semiconductor die including a semiconductor substrate attached to the metallic pad, and a conductor including a sacrificial fuse element above the semiconductor substrate, the sacrificial fuse element being electrically coupled between one of the leads and at least one terminal of the semiconductor die, and a multilayer dielectric between the sacrificial fuse element and the semiconductor substrate, the multilayer dielectric forming one or more planar gaps beneath a profile of the sacrificial fuse element.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: September 12, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Enis Tuncer, Alejandro Hernandez-Luna
  • Publication number: 20220208676
    Abstract: A semiconductor package includes a metallic pad and leads, a semiconductor die including a semiconductor substrate attached to the metallic pad, and a conductor including a sacrificial fuse element above the semiconductor substrate, the sacrificial fuse element being electrically coupled between one of the leads and at least one terminal of the semiconductor die, and a multilayer dielectric between the sacrificial fuse element and the semiconductor substrate, the multilayer dielectric forming one or more planar gaps beneath a profile of the sacrificial fuse element.
    Type: Application
    Filed: December 31, 2020
    Publication date: June 30, 2022
    Inventors: Enis Tuncer, Alejandro Hernandez-Luna
  • Patent number: 11322433
    Abstract: In some examples, a package comprises first and second terminals and a conductive pathway coupling the first and second terminals. The conductive pathway is configured to generate a magnetic field. The package comprises a conductive member aligned with and coupled to the conductive pathway. The conductive pathway and the conductive member have a common shape. The package also comprises an insulative layer coupled to the conductive member and a die coupled to the insulative layer and having a circuit configured to measure the magnetic field. The circuit faces the conductive pathway.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: May 3, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Enis Tuncer, Alejandro Hernandez-Luna
  • Publication number: 20210313258
    Abstract: In some examples, a package comprises first and second terminals and a conductive pathway coupling the first and second terminals. The conductive pathway is configured to generate a magnetic field. The package comprises a conductive member aligned with and coupled to the conductive pathway. The conductive pathway and the conductive member have a common shape. The package also comprises an insulative layer coupled to the conductive member and a die coupled to the insulative layer and having a circuit configured to measure the magnetic field. The circuit faces the conductive pathway.
    Type: Application
    Filed: April 7, 2020
    Publication date: October 7, 2021
    Inventors: Enis TUNCER, Alejandro HERNANDEZ-LUNA
  • Publication number: 20060170081
    Abstract: An electronic packaging combines features of a MAP (molded array package) and a lead frame package. The package includes an electrically conductive substrate somewhat like a lead frame package but defines a grid of conductive pads rather than a multiplicity of leads as is common with a lead frame package. An electronic chip is attached to the top surface of the lead frame, and the output terminals of the electronic chip are individually electrically connected to selected connecting pads of the lead frame grid array. Both flip chips and wire bond chips may be connected to the grid array. The channels defining the grid of connecting pads extend part way through the conductive substrate and increase in width from the top surface of the lead frame to the bottom of the channel such that the molding compound is locked in place when it cures and hardens.
    Type: Application
    Filed: February 3, 2005
    Publication date: August 3, 2006
    Inventors: Mark Gerber, Takahiko Kudoh, Mutsumi Masamoto, Alejandro Hernandez-Luna