Patents by Inventor Alejandro Lenero Beracoechea

Alejandro Lenero Beracoechea has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9864711
    Abstract: Examples are disclosed for automatic downstream to upstream mode switching at a universal serial bus (USB) physical (PHY) layer including activating a switching structure to switch a USB port operating in a downstream mode to an upstream mode based on an attempted attachment by another USB port also operating in a downstream mode. The examples may also include facilitating attachment of the switched USB port now operating in the upstream mode to the other USB port operating in the downstream mode.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: January 9, 2018
    Assignee: INTEL CORPORATION
    Inventors: Jennifer C. Wang, Alejandro Lenero Beracoechea, Nai-Chih Chang, Steven B. McGowan
  • Publication number: 20130275640
    Abstract: Examples are disclosed for automatic downstream to upstream mode switching at a universal serial bus (USB) physical (PHY) layer including activating a switching structure to switch a USB port operating in a downstream mode to an upstream mode based on an attempted attachment by another USB port also operating in a downstream mode. The examples may also include facilitating attachment of the switched USB port now operating in the upstream mode to the other USB port operating in the downstream mode.
    Type: Application
    Filed: December 16, 2011
    Publication date: October 17, 2013
    Inventors: Jennifer C. Wang, Alejandro Lenero Beracoechea, Nai-Chih Chang, Steven B. McGowan
  • Patent number: 8539131
    Abstract: Systems and methods of operating root hub host controllers provide for determining, at a protocol engine having a dedicated port, a speed of a device in response to a coupling of the device to the dedicated port. Data transfer can occur at a second speed between software interface logic of the host controller and the protocol engine, and at the first speed between the protocol engine and the device via the dedicated port, wherein the second speed is greater than the first speed. In addition, data may be transferred in unicast transactions in which no split tokens are exchanged.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: September 17, 2013
    Assignee: Intel Corporation
    Inventors: Nai-Chih Chang, Jennifer C. Wang, Alejandro Lenero Beracoechea
  • Publication number: 20120079145
    Abstract: Systems and methods of operating root hub host controllers provide for determining, at a protocol engine having a dedicated port, a speed of a device in response to a coupling of the device to the dedicated port. Data transfer can occur at a second speed between software interface logic of the host controller and the protocol engine, and at the first speed between the protocol engine and the device via the dedicated port, wherein the second speed is greater than the first speed. In addition, data may be transferred in unicast transactions in which no split tokens are exchanged.
    Type: Application
    Filed: September 23, 2010
    Publication date: March 29, 2012
    Inventors: Nai-Chih Chang, Jennifer C. Wang, Alejandro Lenero Beracoechea
  • Patent number: 7656891
    Abstract: A method and apparatus for processing at least two types of payloads received at varying intervals in a communications network using a single processing path is provided. The two types of payloads may include virtually and contiguously concatenated payloads according to SONET/SHD architecture. The method comprises interleaving data in a predetermined format and controlling distribution of the data irrespective of the format received such that the data can be processed at the destination and passed to downstream components.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: February 2, 2010
    Assignee: Intel Corporation
    Inventors: Juan-Carlos Calderon, Soowan Suh, Jing Ling, Jean-Michel Caia, Alejandro Lenero Beracoechea
  • Patent number: 7460545
    Abstract: A method and apparatus for managing memory for time division multiplexed high speed data traffic is provided. The method and apparatus utilize an interleaving approach in association with multiple memory banks, such as within SDRAM, to perform highly efficient data reading and writing. The design issues a first command or access command, such as a read command or write command to one memory bank, followed by an active command to a second memory bank, enabling efficient reading and writing in a multiple data flow environment, such as a SONET/SDH virtual concatenation environment using differential delay compensation.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: December 2, 2008
    Assignee: Intel Corporation
    Inventors: Juan-Carlos Calderon, Soowan Suh, Jing Ling, Jean-Michel Caia, Augusto Alcantara, Alejandro Lenero Beracoechea