Patents by Inventor Alejandro Martinez Vincente

Alejandro Martinez Vincente has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Merging level cache and data cache units having indicator bits related to speculative execution
    Patent number: 10621092
    Abstract: Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retires instructions of the speculatively executed threads in the MLC.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Fernando Latorre, Josep M. Codina, Enric Gibert Codina, Pedro Lopez, Carlos Madriles, Alejandro Martinez Vincente, Raul Martinez, Antonio Gonzalez
  • Systems, methods, and apparatuses to decompose a sequential program into multiple threads, execute said threads, and reconstruct the sequential execution
    Patent number: 8909902
    Abstract: Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retire instructions of the speculatively executed threads in the MLC.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: December 9, 2014
    Assignee: Intel Corporation
    Inventors: Fernando Latorre, Josep M. Codina, Enric Gibert Codina, Pedro Lopez, Carlos Madriles, Alejandro Martinez Vincente, Raul Martinez, Antonio Gonzalez
  • SYSTEMS, METHODS, AND APPARATUSES TO DECOMPOSE A SEQUENTIAL PROGRAM INTO MULTIPLE THREADS, EXECUTE SAID THREADS, AND RECONSTRUCT THE SEQUENTIAL EXECUTION
    Publication number: 20100269102
    Abstract: Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retire instructions of the speculatively executed threads in the MLC.
    Type: Application
    Filed: November 24, 2009
    Publication date: October 21, 2010
    Inventors: Fernando Latorre, Josep M. Codina, Enric Gibert Codina, Pedro Lopez, Carlos Madriles, Alejandro Martinez Vincente, Raul Martinez, Antonio Gonzalez