Abstract: The invention relates to process for the preparation of gamma valerolactone (GVL) from levulinic acid (LA), said process comprising a) subjecting LA to a hydrogenation reaction comprising hydrogen and a solid catalyst system comprising a metal and a support in the liquid phase, to yield a first reaction mixture comprising GVL, hydroxypentanoic acid (4HPA), and water; b) removing water from said first reaction mixture; and c) subjecting the mixture obtained in step b) to a further reaction under conditions suitable to convert said 4-HPA to GVL, to yield a further reaction mixture. Steps b) and c) can be integrated. Optionally, water can be removed from the further reaction mixture. The process may include recycling the—optionally at least partially dewatered—further reaction mixture back to step (b). This is particularly advantageous when the first reaction mixture is low in, or even free of levulinic acid.

Abstract: The invention relates to process for the preparation of gamma valerolactone (GVL) from levulinic acid (LA), said process comprising a) subjecting LA to a hydrogenation reaction comprising hydrogen and a solid catalyst system comprising a metal and a support in the liquid phase, to yield a first reaction mixture comprising GVL, hydroxypentanoic acid (4HPA), and water; b) removing water from said first reaction mixture; and c) subjecting the mixture obtained in step b) to a further reaction under conditions suitable to convert said 4-HPA to GVL, to yield a further reaction mixture. Steps b) and c) can be integrated. Optionally, water can be removed from the further reaction mixture. The process may include recycling the—optionally at least partially dewatered—further reaction mixture back to step (b). This is particularly advantageous when the first reaction mixture is low in, or even free of levulinic acid.

Abstract: Various embodiments are generally directed toward a viewing device using and steering of collimated light to separately paint detected eye regions of multiple persons to provide them with 3D imagery. A viewing device includes an image panel to cause collimated light to convey multiple pixels of one of a left side frame and a right side frame associated with a frame of 3D imagery, and a steering assembly to steer the collimated light towards an eye to paint an eye region of a face that includes the eye. Other embodiments are described and claimed herein.

Abstract: Techniques are provided for efficient lithography processing and wafer layout. In particular, the techniques can be used to reduce the number of sacrificial exposures along the wafer perimeter region. In one example embodiment, an exposure system reticle is configured with both a normal area (die yielding area) and a dumification area (non-yielding area at wafer perimeter), thereby allowing for lithographic processing in the non-yielding areas sufficient to facilitate successful processing in the adjacent die yielding areas, but without requiring additional sacrificial exposures. This reduction in sacrificial exposures translates to a significant improvement in fab capacity. The techniques can be implemented, for example, on any number of lithography tools having an adjustable reticle or reticle blind capability and in the context of any technology nodes, such as 95 nm and smaller. The lithography tool may produce wafers at a faster rate.

Abstract: Techniques are provided for efficient wafer layout, which include the use of an offset grid to optimize use of available wafer space. As such, the number of identical die that can be fabricated on the wafer can be increased, relative to a standard perpendicular grid. By adding additional registration marks, an increase in flexibility of where each row/column of fields can be printed is enabled. This increased level of freedom in-turn allows for the optimization of the number of die that each row/column can contain, and translates directly into an increase in the number of yielding die per wafer. In addition, techniques are provided that allow for the dicing of individual die in a non-Cartesian coordinated manner. However, conventional singulation techniques can be used as well, given attention to the offset grid lines.

Abstract: Techniques are provided for efficient wafer layout, which include the use of an offset grid to optimize use of available wafer space. As such, the number of identical die that can be fabricated on the wafer can be increased, relative to a standard perpendicular grid. By adding additional registration marks, an increase in flexibility of where each row/column of fields can be printed is enabled. This increased level of freedom in-turn allows for the optimization of the number of die that each row/column can contain, and translates directly into an increase in the number of yielding die per wafer. In addition, techniques are provided that allow for the dicing of individual die in a non-Cartesian coordinated manner. However, conventional singulation techniques can be used as well, given attention to the offset grid lines.