Patents by Inventor Alejandro Varela

Alejandro Varela has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140176684
    Abstract: Various embodiments are generally directed toward a viewing device using and steering of collimated light to separately paint detected eye regions of multiple persons to provide them with 3D imagery. A viewing device includes an image panel to cause collimated light to convey multiple pixels of one of a left side frame and a right side frame associated with a frame of 3D imagery, and a steering assembly to steer the collimated light towards an eye to paint an eye region of a face that includes the eye. Other embodiments are described and claimed herein.
    Type: Application
    Filed: December 24, 2012
    Publication date: June 26, 2014
    Inventors: ALEJANDRO VARELA, BRANDON C. BARNETT
  • Publication number: 20120162622
    Abstract: Techniques are provided for efficient lithography processing and wafer layout. In particular, the techniques can be used to reduce the number of sacrificial exposures along the wafer perimeter region. In one example embodiment, an exposure system reticle is configured with both a normal area (die yielding area) and a dumification area (non-yielding area at wafer perimeter), thereby allowing for lithographic processing in the non-yielding areas sufficient to facilitate successful processing in the adjacent die yielding areas, but without requiring additional sacrificial exposures. This reduction in sacrificial exposures translates to a significant improvement in fab capacity. The techniques can be implemented, for example, on any number of lithography tools having an adjustable reticle or reticle blind capability and in the context of any technology nodes, such as 95 nm and smaller. The lithography tool may produce wafers at a faster rate.
    Type: Application
    Filed: December 23, 2010
    Publication date: June 28, 2012
    Inventors: Alejandro Varela, Michael A. Maxim, Daniel E. Vanlare, Adi Lazar
  • Patent number: 8148239
    Abstract: Techniques are provided for efficient wafer layout, which include the use of an offset grid to optimize use of available wafer space. As such, the number of identical die that can be fabricated on the wafer can be increased, relative to a standard perpendicular grid. By adding additional registration marks, an increase in flexibility of where each row/column of fields can be printed is enabled. This increased level of freedom in-turn allows for the optimization of the number of die that each row/column can contain, and translates directly into an increase in the number of yielding die per wafer. In addition, techniques are provided that allow for the dicing of individual die in a non-Cartesian coordinated manner. However, conventional singulation techniques can be used as well, given attention to the offset grid lines.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: April 3, 2012
    Assignee: Intel Corporation
    Inventors: Alejandro Varela, Troy L. Harling, Daniel E. Vanlare
  • Publication number: 20110147897
    Abstract: Techniques are provided for efficient wafer layout, which include the use of an offset grid to optimize use of available wafer space. As such, the number of identical die that can be fabricated on the wafer can be increased, relative to a standard perpendicular grid. By adding additional registration marks, an increase in flexibility of where each row/column of fields can be printed is enabled. This increased level of freedom in-turn allows for the optimization of the number of die that each row/column can contain, and translates directly into an increase in the number of yielding die per wafer. In addition, techniques are provided that allow for the dicing of individual die in a non-Cartesian coordinated manner. However, conventional singulation techniques can be used as well, given attention to the offset grid lines.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Inventors: Alejandro Varela, Troy L. Harling, Daniel E. Vanlare