Abstract: Techniques related to image distortion correction for images captured by using a wide-angle lens include homography and a lens distortion correction using a radial-ratio-based look up table.

Abstract: Techniques related to image distortion correction for images captured by using a wide-angle lens include homography and a lens distortion correction using a radial-ratio-based look up table.

Abstract: An electronic apparatus may be provided that includes a processor to perform operations, and a memory subsystem including a plurality of parallel memory banks to store a two-dimensional (2D) array of data using a shifted scheme. Each memory bank may include at least two elements per bank word.

Abstract: An example apparatus for processing scattered data includes an address buffer to receive a plurality of vector addresses corresponding to input vector data comprising scattered samples to be processed. The apparatus also includes a multi-bank memory to receive the input vector data and send output vector data. The apparatus further includes a memory controller comprising an address scheduler to assign an address to each bank of the multi-bank memory.

Abstract: An apparatus for localized and random data access is described herein. The apparatus includes a multi-bank memory, a queue, and an output buffer. The multi-bank memory is to store addresses locations of imaging data. The queue corresponds to each bank of the multi-bank memory, and the queue is to store addresses from the multi-bank memory for data access. The output buffer is to store data accessed based on addresses from the queue.

Abstract: High dynamic range image composition is described using multiple images. Some embodiments relate to a system with a buffer to receive each of three different images of a scene, each image having a different amount of light exposure to the scene, as general purpose processor to estimate the alignment between the three images, and an imaging processor to warp the images based on the estimated alignment and to combine the three images to produce a single high dynamic range image.

Abstract: An electronic apparatus may be provided that includes a processor to perform operations, and a memory subsystem including a plurality of parallel memory banks to store a two-dimensional (2D) array of data using a shifted scheme. Each memory bank may include at least two elements per bank word.

Abstract: Technologies are presented that allow efficient pixel-based image and/or video warping and scaling. An image processing system may include a memory and an accelerator unit communicatively coupled with the memory. The accelerator unit may, based on configuration settings, receive, from a memory, at least a portion of an input image as an array of neighboring four-cornered shapes; and process each shape by: determining locations of an array of output pixels delineated by four corner locations of the shape via linearization; interpolating a value of each pixel of the array of output pixels; and storing the interpolated pixel values in the memory. For warping, the array of neighboring four-cornered shapes may include an array of neighboring distorted tetragons that approximate distortion of the input image, and the interpolated pixel values may represent a warped output image. For scaling, the array of neighboring four-cornered shapes may include an array of neighboring rectangles.

Abstract: A data processing system is provided for processing video data on a window basis. At least one memory unit (L1) is provided for fetching and storing video data from an image memory (IM) according to a first window (R) in a first scanning order. At least one second memory unit (L0) is provided for fetching and storing video data from the first memory unit (L1) according to a second window in a second scanning order (SO). Furthermore, at least one processing unit (PU) is provided for performing video processing on the video data of the second window as stored in the at least one second memory unit (L0) based on the second scanning order (SO). The second scanning order (SO) is a meandering scanning order being orthogonal to the first scanning order (SO1).

Abstract: Methods, apparatus, systems and articles of manufacture to perform block-based static region detection for video processing are disclosed. Disclosed example video processing methods include segmenting pixels in a first frame of a video sequence into a first plurality of pixel blocks. Such example methods can also include processing the first plurality of pixel blocks and a second plurality of pixel blocks corresponding to a prior second frame of the video sequence to create, based on a first criterion, a map identifying one or more static pixel blocks in the first plurality of pixel blocks. Such example methods can further include identifying, based on the map, a static region in the first frame of the video sequence.

Abstract: An electronic apparatus may be provided that includes a processor to perform operations, and a memory subsystem including a plurality of parallel memory banks to store a two-dimensional (2D) array of data using a shifted scheme. Each memory bank may include at least two elements per bank word.

Abstract: High dynamic range image composition is described using multiple images. Some embodiments relate to a system with a buffer to receive each of three different images of a scene, each image having a different amount of light exposure to the scene, as general purpose processor to estimate the alignment between the three images, and an imaging processor to warp the images based on the estimated alignment and to combine the three images to produce a single high dynamic range image.

Abstract: Techniques related to managing the use of motion estimation in video processing are discussed. Such techniques may include determining dividing two video frames each into corresponding regions, generating phase plane correlations for the corresponding regions, determining whether the video frames are motion estimation correlated based on the phase plane correlations, and providing a video frame prediction mode indicator based on the determination.

Abstract: Technologies are presented that allow efficient pixel-based image and/or video warping and scaling. An image processing system may include a memory and an accelerator unit communicatively coupled with the memory. The accelerator unit may, based on configuration settings, receive, from a memory, at least a portion of an input image as an array of neighboring four-cornered shapes; and process each shape by: determining locations of an array of output pixels delineated by four corner locations of the shape via linearization; interpolating a value of each pixel of the array of output pixels; and storing the interpolated pixel values in the memory. For warping, the array of neighboring four-cornered shapes may include an array of neighboring distorted tetragons that approximate distortion of the input image, and the interpolated pixel values may represent a warped output image. For scaling, the array of neighboring four-cornered shapes may include an array of neighboring rectangles.

Abstract: Methods, apparatus, systems and articles of manufacture to perform block-based static region detection for video processing are disclosed. Disclosed example video processing methods include segmenting pixels in a first frame of a video sequence into a first plurality of pixel blocks. Such example methods can also include processing the first plurality of pixel blocks and a second plurality of pixel blocks corresponding to a prior second frame of the video sequence to create, based on a first criterion, a map identifying one or more static pixel blocks in the first plurality of pixel blocks. Such example methods can further include identifying, based on the map, a static region in the first frame of the video sequence.

Abstract: Techniques related to managing the use of motion estimation in video processing are discussed. Such techniques may include determining dividing two video frames each into corresponding regions, generating phase plane correlations for the corresponding regions, determining whether the video frames are motion estimation correlated based on the phase plane correlations, and providing a video frame prediction mode indicator based on the determination.

Abstract: Systems, apparatus, articles, and methods are described related to motion estimation using hierarchical phase plane correlation and block matching.

Abstract: An electronic apparatus may be provided that includes a processor to perform operations, and a memory subsystem including a plurality of parallel memory banks to store a two-dimensional (2D) array of data using a shifted scheme. Each memory bank may include at least two elements per bank word.

Abstract: A data buffering device which contains an input unit adapted to sequentially receive a two-dimensional array of data structures organized by an index pair with a first index stepwise traversing first-index values in a meandering manner defined by a first and a second meandering direction. The invention further includes a data buffering method, and a data processing method and device; each of which incorporates the above described features of the data buffering device.

Abstract: An array of data values, such as an image of pixel values, is stored in a main memory (12). A processing operation is performed using the pixel values. The processing operation defines time points of movement of a multidimensional region (20, 22) of locations in the image. Pixel values from inside and around the region are cached for processing. At least when a cache miss occurs for a pixel value from outside the region, cache replacement of data in cache locations (142) is performed. Locations that store pixel data for locations in the image outside the region (20, 22) are selected for replacement, selectively exempting from replacement cache locations (142) that store pixel data locations in the image inside the region. In embodiments, different types of cache structure are used for caching data values inside and outside the region. In an embodiment the cache locations for pixel data inside the regions support a higher level of output parallelism than the cache locations for pixel data around the region.