Patents by Inventor Aleksandar Cejkov

Aleksandar Cejkov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210382716
    Abstract: A processing core and associated methods for the efficient execution of a directed graph are disclosed. A disclosed processing core includes a memory and a first data tile stored in the memory. The first data tile includes a first set of data elements and metadata stored in association with the first set of data elements. The processing core also includes a second data tile stored in the memory. The second data tile includes a second set of data elements. The processing core also includes an arithmetic logic unit configured to conduct an arithmetic logic operation using data from the first set of data elements and the second set of data elements. The processing core also includes a control unit configured to evaluate the metadata and control the arithmetic logic unit to conditionally execute the arithmetic logic operation based on the evaluation of the metadata.
    Type: Application
    Filed: August 23, 2021
    Publication date: December 9, 2021
    Applicant: Tenstorrent Inc.
    Inventors: Ljubisa Bajic, Milos Trajkovic, Ivan Hamer, Lejla Bajic, Aleksandar Cejkov
  • Patent number: 11113051
    Abstract: A processing core and associated methods for the efficient execution of a directed graph are disclosed. A disclosed processing core comprises a memory and a first data tile stored in the memory. The first data tile includes a first set of data elements and metadata stored in association with the first set of data elements. The processing core also comprises a second data tile stored in the memory. The second data tile includes a second set of data elements. The processing core also comprises an arithmetic logic unit configured to conduct an arithmetic logic operation using data from the first set of data elements and the second set of data elements. The processing core also comprises a control unit configured to evaluate the metadata and control the arithmetic logic unit to conditionally execute the arithmetic logic operation based on the evaluation of the metadata.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: September 7, 2021
    Assignee: Tenstorrent Inc.
    Inventors: Ljubisa Bajic, Milos Trajkovic, Ivan Hamer, Lejla Bajic, Aleksandar Cejkov
  • Publication number: 20190050224
    Abstract: A processing core and associated methods for the efficient execution of a directed graph are disclosed. A disclosed processing core comprises a memory and a first data tile stored in the memory. The first data tile includes a first set of data elements and metadata stored in association with the first set of data elements. The processing core also comprises a second data tile stored in the memory. The second data tile includes a second set of data elements. The processing core also comprises an arithmetic logic unit configured to conduct an arithmetic logic operation using data from the first set of data elements and the second set of data elements. The processing core also comprises a control unit configured to evaluate the metadata and control the arithmetic logic unit to conditionally execute the arithmetic logic operation based on the evaluation of the metadata.
    Type: Application
    Filed: October 8, 2018
    Publication date: February 14, 2019
    Applicant: Tenstorrent Inc.
    Inventors: Ljubisa Bajic, Milos Trajkovic, Ivan Hamer, Lejla Bajic, Aleksandar Cejkov