Abstract: Methods and apparatus are disclosed low power motion detection by a radar apparatus. One example radar apparatus includes a transmitter to transmit a pattern of chirps. The transmitted pattern includes a first series of chirps transmitted during a first time period and a second series of chirps transmitted during a second time period that begins after passage of a sleep time period from an end of the first time period. The example radar apparatus also includes a receiver to detect returning chirps including reflected portions of the transmitted pattern. The example radar apparatus also includes analog to digital converter (ADC) coupled to the receiver. The ADC is to sample analog signals from the receiver to generate ADC samples for the returning chirps detected by the receiver.

Abstract: A wireless device includes a preamble detector configured to identify a plurality of preambles transmitted via a random access channel of a wireless network. The preamble detector includes a noise floor estimator. The noise floor estimator is configured to: estimate, for a given preamble root sequence identified by the preamble detector, a noise floor value as mean energy of received signal samples, excluding detected preamble samples on the give preamble root sequence, below a noise floor threshold assigned to the given preamble root sequence. The noise floor estimator is configured to compute the noise floor threshold as a product of: average energy of the received signal samples less total signal energy contained in each cyclic prefix window in which a preamble is detected using the given preamble root sequence; and a predetermined normalized relative noise floor threshold based on a target false preamble detection rate.

Abstract: A wireless device includes a preamble detector configured to identify preambles transmitted via a random access channel of a wireless network. The preamble detector includes preamble false alarm logic. The preamble false alarm logic is configured to set a preamble false alarm detection window, and compare, to one another, preambles identified in the false alarm detection window. The preamble false alarm logic is configured to identify, based on the comparison, a largest of the preambles in the false alarm detection window, and reject all but the identified largest of the preambles as false alarm detections.

Abstract: A wireless device includes a preamble detector configured to identify preambles transmitted via a random access channel of a wireless network. The preamble detector includes preamble false alarm logic. The preamble false alarm logic is configured to set a preamble false alarm detection window, and compare, to one another, preambles identified in the false alarm detection window. The preamble false alarm logic is configured to identify, based on the comparison, a largest of the preambles in the false alarm detection window, and reject all but the identified largest of the preambles as false alarm detections.

Abstract: A wireless device includes a preamble detector configured to identify a plurality of preambles transmitted via a random access channel of a wireless network. The preamble detector includes a noise floor estimator. The noise floor estimator is configured to: estimate, for a given preamble root sequence identified by the preamble detector, a noise floor value as mean energy of received signal samples, excluding detected preamble samples on the give preamble root sequence, below a noise floor threshold assigned to the given preamble root sequence. The noise floor estimator is configured to compute the noise floor threshold as a product of: average energy of the received signal samples less total signal energy contained in each cyclic prefix window in which a preamble is detected using the given preamble root sequence; and a predetermined normalized relative noise floor threshold based on a target false preamble detection rate.

Abstract: A decoding circuit, is provided, comprising: a turbo decoder configured to receive a input systematic bit soft information values and input parity bit information values, and to generate output systematic bit soft information values and hard decoded bits according to a turbo decoding operation; and a parity bit soft information generation circuit configured to receive the input systematic bit soft information values, the input parity bit soft information values, and the output systematic bit soft information values; to determine initial forward metrics, initial backward metrics, and branch metrics as a function of the input parity bit soft information values and the output systematic bit soft information values; to determine output parity bit soft information values based on the branch metrics, the initial forward metrics, and the initial backward metrics; and to provide the output parity bit soft information values as a signal output.

Abstract: Example methods are disclosed for encoding variable sized data using a low-density parity-check (LDPC) code, and transporting the encoded variable sized data in modulated symbols. Example methods involve calculating a minimum number of modulated symbols capable of transmitting a data packet; selecting a codeword size suitable for transmitting the data packet; calculating a number of shortening Nshortened bits; and calculating a number of puncturing Npunctured bits, to thereby produce a shortened and punctured expanded parity check matrix for transmitting the data packet.

Abstract: A method for constructing a low-density parity-check (LDPC) code using a structured base parity check matrix with permutation matrix, pseudo-permutation matrix, or zero matrix as constituent sub-matrices; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for constructing a LDPC code using a structured base parity check matrix H=[Hd|Hp], Hd is the data portion, and Hp is the parity portion of the parity check matrix; the parity portion of the structured base parity check matrix is such so that when expanded, an inverse of the parity portion of the expanded parity check matrix is sparse; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for encoding variable sized data by using the expanded LDPC code; and applying shortening, puncturing.

Abstract: A method for constructing a low-density parity-check (LDPC) code using a structured base parity check matrix with permutation matrix, pseudo-permutation matrix, or zero matrix as constituent sub-matrices; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for constructing a LDPC code using a structured base parity check matrix H=[Hd|Hp], Hd is the data portion, and Hp is the parity portion of the parity check matrix; the parity portion of the structured base parity check matrix is such so that when expanded, an inverse of the parity portion of the expanded parity check matrix is sparse; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for encoding variable sized data by using the expanded LDPC code; and applying shortening, puncturing.

Abstract: A method for constructing a low-density parity-check (LDPC) code using a structured base parity check matrix with permutation matrix, pseudo-permutation matrix, or zero matrix as constituent sub-matrices; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for constructing a LDPC code using a structured base parity check matrix H=[Hd|Hp], Hd is the data portion, and Hp is the parity portion of the parity check matrix; the parity portion of the structured base parity check matrix is such so that when expanded, an inverse of the parity portion of the expanded parity check matrix is sparse; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for encoding variable sized data by using the expanded LDPC code; and applying shortening, puncturing.

Abstract: A method for constructing a low-density parity-check (LDPC) code using a structured base parity check matrix with permutation matrix, pseudo-permutation matrix, or zero matrix as constituent sub-matrices; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for constructing a LDPC code using a structured base parity check matrix H=[Hd|Hp], Hd is the data portion, and Hp is the parity portion of the parity check matrix; the parity portion of the structured base parity check matrix is such so that when expanded, an inverse of the parity portion of the expanded parity check matrix is sparse; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for encoding variable sized data by using the expanded LDPC code; and applying shortening, puncturing.

Abstract: A method for constructing a low-density parity-check (LDPC) code using a structured base parity check matrix with permutation matrix, pseudo-permutation matrix, or zero matrix as constituent sub-matrices; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for constructing a LDPC code using a structured base parity check matrix H=[Hd|Hp], Hd is the data portion, and Hp is the parity portion of the parity check matrix; the parity portion of the structured base parity check matrix is such so that when expanded, an inverse of the parity portion of the expanded parity check matrix is sparse; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for encoding variable sized data by using the expanded LDPC code; and applying shortening, puncturing.

Abstract: A decoding circuit, is provided, comprising: a turbo decoder configured to receive a input systematic bit soft information values and input parity bit information values, and to generate output systematic bit soft information values and hard decoded bits according to a turbo decoding operation; and a parity bit soft information generation circuit configured to receive the input systematic bit soft information values, the input parity bit soft information values, and the output systematic bit soft information values; to determine initial forward metrics, initial backward metrics, and branch metrics as a function of the input parity bit soft information values and the output systematic bit soft information values; to determine output parity bit soft information values based on the branch metrics, the initial forward metrics, and the initial backward metrics; and to provide the output parity bit soft information values as a signal output.

Abstract: The invention introduces an apparatus, method and system that allow coding matrices to be expanded to accommodate various information packet sizes and support for various code rates; additionally the invention defines a number of coding matrices particularly suited to the methodology. The invention enables high throughput implementations, allows achieving low latency, and offers other numerous implementation benefits. At the same time, the new parity part of the matrix preserves the simple (recursive) encoding feature.

Abstract: A technique for reducing peak-to-average power ratio (PAPR) in digital signal communications is disclosed. In one particular exemplary embodiment, the technique may be realized by a method comprising the steps of modulating a frequency-domain input vector comprising a plurality of path vectors by applying a Gray code sequence of combinations of binary phase rotations to the plurality of path vectors, where, in each combination, the binary phase rotation of only one of the plurality of path vectors is changed from a previous combination in the Gray code sequence; and determining an optimal time-domain peak value based on the modulated frequency-domain input vector.

Abstract: A multi-stage signal processing method is provided that reduces the Peak to Average Power Ratio (PAPR) of an Orthogonal Frequency Division Multiplexed (OFDM) signal without increasing the bit error rate of the system. The multi-stage processing system apportions the tones into a number of types, and processes the tones in an order and by a process consistent with their determined type. Advantageously, preprocessing of the time domain signal may be used to condition the data tones for optimal PAPR reduction during the multi-stage process.

Abstract: A higher code rate Low-Density Parity Check (LDPC) matrix may be designed by concatenating additional matrices to a ?-rotation parity check matrix. The concatenated matrix may be selected such that the resultant LDPC matrix exhibits good expansion characteristics to enable the LDPC matrix to be used with variable block length codes. The codes may be designed by generating an ensemble of available codes, encoding them with information vectors of weight 1 and 2 and discarding codes with a low minimum distance. The approximate upper bounds for the remaining codes are then calculated and a small set of codes with the lowest bound under high signal to noise ratio is selected. The girth distributions for the remaining codes are then calculated and the code that has the minimum number of short cycles is selected. The selected code is concatenated to the original ?-rotation parity check matrix.

Abstract: A method for constructing a low-density parity-check (LDPC) code using a structured base parity check matrix with permutation matrix, pseudo-permutation matrix, or zero matrix as constituent sub-matrices; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for constructing a LDPC code using a structured base parity check matrix H=[Hd|Hp], Hd is the data portion, and Hp is the parity portion of the parity check matrix; the parity portion of the structured base parity check matrix is such so that when expanded, an inverse of the parity portion of the expanded parity check matrix is sparse; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for encoding variable sized data by using the expanded LDPC code; and applying shortening, puncturing.

Abstract: A method for constructing a low-density parity-check (LDPC) code using a structured base parity check matrix with permutation matrix, pseudo-permutation matrix, or zero matrix as constituent sub-matrices; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for constructing a LDPC code using a structured base parity check matrix H=[Hd|Hp], Hd is the data portion, and Hp is the parity portion of the parity check matrix; the parity portion of the structured base parity check matrix is such so that when expanded, an inverse of the parity portion of the expanded parity check matrix is sparse; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for encoding variable sized data by using the expanded LDPC code; and applying shortening, puncturing.

Abstract: A method for constructing a low-density parity-check (LDPC) code using a structured base parity check matrix with permutation matrix, pseudo-permutation matrix, or zero matrix as constituent sub-matrices; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for constructing a LDPC code using a structured base parity check matrix H=[Hd|Hp], Hd is the data portion, and Hp is the parity portion of the parity check matrix; the parity portion of the structured base parity check matrix is such so that when expanded, an inverse of the parity portion of the expanded parity check matrix is sparse; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for encoding variable sized data by using the expanded LDPC code; and applying shortening, puncturing. System and method for operating a wireless device to encode data using low-density parity-check (LDPC) encoding is discussed.