Abstract: Technologies are generally described for an array of logic elements effective to generate a data signal. A first logic element may include an input circuit, a comparator circuit, and a state machine. The input circuit may receive a first input state signal and a second input state signal from a second logic element and a third logic element, respectively. The input circuit may determine a sum based on the first and second input state signals. The comparator circuit may compare the sum with a threshold and, in response, may generate an intermediate signal based on the comparison. The state machine may identify a current state of the first logic element. The state machine may generate an output state signal based on the intermediate signal and the current state of the first logic element. The output state signal may indicate a subsequent state of the first logic element.

Abstract: Technologies are generally described for an array of logic elements effective to generate a data signal. A first logic element may include an input circuit, a comparator circuit, and a state machine. The input circuit may receive a first input state signal and a second input state signal from a second logic element and a third logic element, respectively. The input circuit may determine a sum based on the first and second input state signals. The comparator circuit may compare the sum with a threshold and, in response, may generate an intermediate signal based on the comparison. The state machine may identify a current state of the first logic element. The state machine may generate an output state signal based on the intermediate signal and the current state of the first logic element. The output state signal may indicate a subsequent state of the first logic element.